[PATCH 2/2] pwm: meson: Fix computing counter register

[George Stark]

High and low values in the counter register are incremented by 1
internally unless they a zero and constant bit is supported and set.
So decrement by 1 calculated high and low PWM periods before applying.

Signed-off-by: George Stark <gnstark@xxxxxxxxxxxxxxxxx>
---
 drivers/pwm/pwm-meson.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
index 8c6bf3d49753..51839936ec89 100644
--- a/drivers/pwm/pwm-meson.c
+++ b/drivers/pwm/pwm-meson.c
@@ -214,6 +214,15 @@ static int meson_pwm_calc(struct pwm_chip *chip, struct pwm_device *pwm,
 		channel->hi = duty_cnt;
 		channel->lo = cnt - duty_cnt;
 		channel->constant = false;
+
+		/*
+		 * hi and low reg values are incremented by 1 internally
+		 * unless they are zero and constant bit is set
+		 */
+		if (channel->hi)
+			channel->hi--;
+		if (channel->lo)
+			channel->lo--;
 	}

 	channel->rate = fin_freq;
@@ -342,6 +351,7 @@ static int meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 	struct meson_pwm *meson = to_meson_pwm(chip);
 	struct meson_pwm_channel_data *channel_data;
 	unsigned long fin_freq;
+	bool const_enabled;
 	unsigned int hi, lo;
 	u32 value;

@@ -356,10 +366,16 @@ static int meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 	else
 		state->polarity = PWM_POLARITY_NORMAL;

+	const_enabled = meson->data->has_constant &&
+		(value & channel_data->const_en_mask);
+
 	value = readl(meson->base + channel_data->reg_offset);
 	lo = FIELD_GET(PWM_LOW_MASK, value);
 	hi = FIELD_GET(PWM_HIGH_MASK, value);

+	lo += (const_enabled ? !!lo : 1);
+	hi += (const_enabled ? !!hi : 1);
+
 	state->period = meson_pwm_cnt_to_ns(fin_freq, lo + hi);
 	state->duty_cycle = meson_pwm_cnt_to_ns(fin_freq, hi);

--
2.25.1