Re: [PATCH] arm64: dts: ti: k3-am69-sk: Add USB SuperSpeed support

[Roger Quadros]

Hi Enric,

On 26/11/2024 12:08, Enric Balletbo i Serra wrote:
> From: Dasnavis Sabiya <sabiya.d@xxxxxx>
> 
> AM69 SK board has two stacked USB3 connectors:
>    1. USB3 (Stacked TypeA + TypeC)
>    2. USB3 TypeA Hub interfaced through TUSB8041.
> 
> The board uses SERDES0 Lane 3 for USB3 IP. So update the
> SerDes lane info for PCIe and USB. Add the pin mux data
> and enable USB 3.0 support with its respective SERDES settings.
> 
> Signed-off-by: Dasnavis Sabiya <sabiya.d@xxxxxx>
> Signed-off-by: Enric Balletbo i Serra <eballetb@xxxxxxxxxx>
> ---
> I've been carrying this patch for quite long time in my builds to have
> support for USB on my AM69-SK board without problems. For some reason this
> patch was never send to upstream or I couldn't find it. So I took the
> opportunity, now that I rebased my build, to send upstream.
> 
> I have maintained the original author of the downstream patch as is
> basically his work.
> ---
>  arch/arm64/boot/dts/ti/k3-am69-sk.dts | 33 +++++++++++++++++++++++++++++++++
>  1 file changed, 33 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
> index 1e36965a14032ca07143230855e04b9549f1d0d1..72797f4b689c1d069bf395d6d4fe1846dc4e4297 100644
> --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
> @@ -484,6 +484,12 @@ J784S4_IOPAD(0x09C, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */
>  		>;
>  	};
>  
> +	main_usbss0_pins_default: main-usbss0-default-pins {
> +		pinctrl-single,pins = <
> +			J784S4_IOPAD(0x0EC, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */

address offset should be lower case?

> +		>;
> +	};
> +
>  };
>  
>  &wkup_pmx0 {
> @@ -1299,6 +1305,14 @@ serdes0_pcie_link: phy@0 {
>  		cdns,phy-type = <PHY_TYPE_PCIE>;
>  		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>, <&serdes_wiz0 3>;
>  	};
> +
> +	serdes0_usb_link: phy@3 {
> +		reg = <3>;
> +		cdns,num-lanes = <1>;
> +		#phy-cells = <0>;
> +		cdns,phy-type = <PHY_TYPE_USB3>;
> +		resets = <&serdes_wiz0 4>;
> +	};
>  };
>  
>  &serdes_wiz1 {
> @@ -1339,3 +1353,22 @@ &pcie3_rc {
>  	phy-names = "pcie-phy";
>  	num-lanes = <1>;
>  };
> +
> +&usb_serdes_mux {
> +	idle-states = <0>; /* USB0 to SERDES0 */
> +};
> +
> +&usbss0 {
> +	status = "okay";
> +	pinctrl-0 = <&main_usbss0_pins_default>;
> +	pinctrl-names = "default";
> +	ti,vbus-divider;
> +};
> +
> +&usb0 {
> +	status = "okay";
> +	dr_mode = "host";
> +	maximum-speed = "super-speed";
> +	phys = <&serdes0_usb_link>;
> +	phy-names = "cdns3,usb3-phy";
> +};

Reviewed-by: Roger Quadros <rogerq@xxxxxxxxxx>

-- 
cheers,
-roger