Re: (subset) [PATCH v2 0/6] Correct the number of GPIOs in gpio-ranges for QCS615 and QCS8300

[Bjorn Andersson]

On Thu, 19 Dec 2024 15:59:42 +0800, Lijuan Gao wrote:
> The UFS_RESET pin on Qualcomm SoCs are controlled by TLMM and exposed
> through the GPIO framework. It is expected to be wired to the reset pin
> of the primary UFS memory so that the UFS driver can toggle it.
> 
> The UFS_RESET pin is exported as GPIOs in addtion to the real GPIOs. The
> QCS615 TLMM pin controller has GPIOs 0-122, so correct the gpio-rangs to
> 124. The QCS8300 TLMM pin controller has GPIOs 0-132, so correct the
> gpio-rangs to 134.
> 
> [...]

Applied, thanks!

[5/6] arm64: dts: qcom: correct gpio-ranges for QCS615
      commit: 80c82827327d80bde8fc96ebd4e637d0454062db
[6/6] arm64: dts: qcom: correct gpio-ranges for QCS8300
      commit: c57c39ee522d873db2cb23486581a8269c389cfe

Best regards,
-- 
Bjorn Andersson <andersson@xxxxxxxxxx>