Re: [PATCH RFC 08/11] drm/msm/dsi: Add support for SM8750

[Krzysztof Kozlowski]

On 10/01/2025 10:17, Dmitry Baryshkov wrote:
> On Fri, Jan 10, 2025 at 09:59:26AM +0100, Krzysztof Kozlowski wrote:
>> On 10/01/2025 00:18, Dmitry Baryshkov wrote:
>>> On Thu, Jan 09, 2025 at 02:08:35PM +0100, Krzysztof Kozlowski wrote:
>>>> Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with two
>>>> differences worth noting:
>>>>
>>>> 1. ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their
>>>>    offsets were just switched.  Currently these registers are not used
>>>>    in the driver, so the easiest is to document both but keep them
>>>>    commented out to avoid conflict.
>>>>
>>>> 2. DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as
>>>>    parents before they are prepared and initial rate is set.  Therefore
>>>>    assigned-clock-parents are not working here and driver is responsible
>>>>    for reparenting clocks with proper procedure: see dsi_clk_init_6g_v2_9().
>>>
>>> Isn't it a description of CLK_SET_PARENT_GATE and/or
>>
>> No - must be gated accross reparent - so opposite.
>>
>>> CLK_OPS_PARENT_ENABLE ?
>>
>> Yes, but does not work. Probably enabling parent, before
>> assigned-clocks-parents, happens still too early:
>>
>> [    1.623554] DSI PLL(0) lock failed, status=0x00000000
>> [    1.623556] PLL(0) lock failed
>> [    1.624650] ------------[ cut here ]------------
>> [    1.624651] disp_cc_mdss_byte0_clk_src: rcg didn't update its
>> configuration.
>>
>> Or maybe something is missing in the DSI PHY PLL driver?
> 
> Do you have the no-zero-freq workaround?

Yes, it is necessary also for my variant. I did not include it here, but
I should mention it in the cover letter.

Best regards,
Krzysztof