[PATCH v2] pinctrl: renesas: rzg2l: Update PFC_MASK to align with RZ/V2H requirements

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>

The PFC_MASK value for the PFC_mx register was previously hardcoded as
`0x07`, which is correct for SoCs in the RZ/G2L family but insufficient
for RZ/V2H and RZ/G3E, where the mask value should be `0x0f`. This
discrepancy caused incorrect PFC register configurations on RZ/V2H and
RZ/G3E SoCs.

On the RZ/G2L, the PFC_mx bitfields are also 4 bits wide, with bit 4
marked as reserved. The reserved bits are documented to read as zero and
be ignored when written. Updating the PFC_MASK definition from `0x07` to
`0x0f` ensures compatibility with both SoC families while maintaining
correct behavior on RZ/G2L.

Fixes: 9bd95ac86e70 ("pinctrl: renesas: rzg2l: Add support for RZ/V2H SoC")
Cc: stable@xxxxxxxxxxxxxxx
Reported-by: Hien Huynh <hien.huynh.px@xxxxxxxxxxx>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
---
v1->v2
- Dropped SoC specific configuration
---
 drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index ffcc5255724d..e33efd65670f 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -159,7 +159,7 @@
 #define PWPR_REGWE_B		BIT(5)	/* OEN Register Write Enable, known only in RZ/V2H(P) */
 
 #define PM_MASK			0x03
-#define PFC_MASK		0x07
+#define PFC_MASK		0x0f
 #define IEN_MASK		0x01
 #define IOLH_MASK		0x03
 #define SR_MASK			0x01
-- 
2.43.0