Re: [RFC PATCH v1 2/3] riscv: dts: starfive: jh7110: add DRAM memory controller node

[Conor Dooley]

On Thu, Jan 02, 2025 at 12:41:22PM -0800, E Shattow wrote:
> add DRAM memory controller node (no driver), required for U-Boot to boot
> successfully.
> 
> Signed-off-by: E Shattow <e@xxxxxxxxxxxx>
> ---
>  arch/riscv/boot/dts/starfive/jh7110.dtsi | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index 0bc922b3ae8a..6948974400c1 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -381,6 +381,19 @@ ccache: cache-controller@2010000 {
>  			cache-unified;
>  		};
>  
> +		dmc: dmc@15700000 {

memory-controller@157.... cos you don't need the label and "dmc" isn't
generic. You're missing a binding for this either way.

> +			compatible = "starfive,jh7110-dmc";


> +			reg = <0x0 0x15700000 0x0 0x10000>,
> +			      <0x0 0x13000000 0x0 0x10000>;
> +			resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
> +				 <&syscrg JH7110_SYSRST_DDR_OSC>,
> +				 <&syscrg JH7110_SYSRST_DDR_APB>;
> +			reset-names = "axi", "osc", "apb";
> +			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
> +			clock-names = "pll1_out";
> +			clock-frequency = <2133>;
> +		};
> +
>  		plic: interrupt-controller@c000000 {
>  			compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
>  			reg = <0x0 0xc000000 0x0 0x4000000>;
> -- 
> 2.45.2
>

Attachment: signature.asc
Description: PGP signature