Re: [PATCH v4 11/12] x86/mm: enable AMD translation cache extensions

[Rik van Riel]

On Mon, 2025-01-13 at 11:32 +0000, Andrew Cooper wrote:
> >  +++
> > b/arch/x86/kernel/cpu/amd.c @@ -1071,6 +1071,9 @@ static void
> > init_amd(struct cpuinfo_x86 *c)  
> >  	/* AMD CPUs don't need fencing after x2APIC/TSC_DEADLINE
> > MSR writes. */
> >  	clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE);
> > + + if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) +
> > msr_set_bit(MSR_EFER, _EFER_TCE);  }
> >  
> >  #ifdef CONFIG_X86_32
> 
> I don't think this is wise.  TCE is orthogonal to INVLPGB.
> 
> Either Linux is safe with TCE turned on, and it should be turned on
> everywhere (it goes back to Fam10h CPUs IIRC), or Linux isn't safe
> with
> TCE turned on, and this needs to depend on some other condition.
> 
> Or, is this a typo and did you mean to check the TCE CPUID bit,
> rather
> than the INVLPGB CPUID bit?

You're right, this should just check against X86_FEATURE_TCE,
which I did not realize was a separate feature bit.

I've changed this for the next version of the series.

Thank you!

-- 
All Rights Reversed.