Re: [PATCH 5/5] irqchip/aclint-sswi: Use wmb() to order normal writes and IPI writes

[Anup Patel]

On Mon, Jan 13, 2025 at 8:40 PM Xu Lu <luxu.kernel@xxxxxxxxxxxxx> wrote:
>
> During an IPI procedure, we need to ensure all previous write operations
> are visible to other CPUs before sending a real IPI. We use wmb() barrier
> to ensure this as ACLINT SSWI issues IPI via mmio writes.
>
> Signed-off-by: Xu Lu <luxu.kernel@xxxxxxxxxxxxx>
> ---
>  drivers/irqchip/irq-thead-c900-aclint-sswi.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/irqchip/irq-thead-c900-aclint-sswi.c b/drivers/irqchip/irq-thead-c900-aclint-sswi.c
> index b0e366ade427..7246a008a0f0 100644
> --- a/drivers/irqchip/irq-thead-c900-aclint-sswi.c
> +++ b/drivers/irqchip/irq-thead-c900-aclint-sswi.c
> @@ -31,6 +31,12 @@ static DEFINE_PER_CPU(void __iomem *, sswi_cpu_regs);
>
>  static void thead_aclint_sswi_ipi_send(unsigned int cpu)
>  {
> +       /*
> +        * Ensure that stores to normal memory are visible to the other CPUs
> +        * before issuing IPI.
> +        */
> +       wmb();
> +

Same comment as PATCH3.

The thead_aclint_sswi_ipi_send() is called through ipi_mux_send_mask()
which does smp_mb__after_atomic() before calling so no need
for any barrier here. Also, barriers need to be in-pair so adding
a single barrier at random location is inappropriate.
(Refer, https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/kernel/irq/ipi-mux.c?h=v6.13-rc7#n78)

Based on the above, this patch is not needed.

Regards,
Anup