[GIT PULL] KVM: x86: VMX change for 6.14

From: Sean Christopherson
Date: Thu Jan 16 2025 - 20:10:38 EST


A few fixes and cleanups. The most notable change is Chao's fix for a nasty
bug where L1's SVI didn't get updated and result in the interrupt being left
in-service forever (though only uncommon use cases are affected, e.g. running
pKVM x86 in L1).

The following changes since commit 3522c419758ee8dca5a0e8753ee0070a22157bc1:

Merge tag 'kvm-riscv-fixes-6.13-1' of https://github.com/kvm-riscv/linux into HEAD (2024-12-13 13:59:20 -0500)

are available in the Git repository at:

https://github.com/kvm-x86/linux.git tags/kvm-x86-vmx-6.14

for you to fetch changes up to 37c3ddfe5238d88b6ec091ecdf967848bce067c2:

KVM: VMX: read the PML log in the same order as it was written (2025-01-08 14:31:25 -0800)

----------------------------------------------------------------
KVM VMX changes for 6.14:

- Fix a bug where KVM updates hardware's APICv cache of the highest ISR bit
while L2 is active, while ultimately results in a hardware-accelerated L1
EOI effectively being lost.

- Honor event priority when emulating Posted Interrupt delivery during nested
VM-Enter by queueing KVM_REQ_EVENT instead of immediately handling the
interrupt.

- Drop kvm_x86_ops.hwapic_irr_update() as KVM updates hardware's APICv cache
prior to every VM-Enter.

- Rework KVM's processing of the Page-Modification Logging buffer to reap
entries in the same order they were created, i.e. to mark gfns dirty in the
same order that hardware marked the page/PTE dirty.

- Misc cleanups.

----------------------------------------------------------------
Adrian Hunter (1):
KVM: VMX: Allow toggling bits in MSR_IA32_RTIT_CTL when enable bit is cleared

Chao Gao (2):
KVM: nVMX: Defer SVI update to vmcs01 on EOI when L2 is active w/o VID
KVM: x86: Remove hwapic_irr_update() from kvm_x86_ops

Costas Argyris (1):
KVM: VMX: Reinstate __exit attribute for vmx_exit()

Gao Shiyuan (1):
KVM: VMX: Fix comment of handle_vmx_instruction()

Maxim Levitsky (2):
KVM: VMX: refactor PML terminology
KVM: VMX: read the PML log in the same order as it was written

Sean Christopherson (6):
KVM: x86: Plumb in the vCPU to kvm_x86_ops.hwapic_isr_update()
KVM: nVMX: Explicitly update vPPR on successful nested VM-Enter
KVM: nVMX: Check for pending INIT/SIPI after entering non-root mode
KVM: nVMX: Drop manual vmcs01.GUEST_INTERRUPT_STATUS.RVI check at VM-Enter
KVM: nVMX: Use vmcs01's controls shadow to check for IRQ/NMI windows at VM-Enter
KVM: nVMX: Honor event priority when emulating PI delivery during VM-Enter

arch/x86/include/asm/kvm-x86-ops.h | 1 -
arch/x86/include/asm/kvm_host.h | 3 +-
arch/x86/kvm/lapic.c | 25 +++++++-----
arch/x86/kvm/lapic.h | 1 +
arch/x86/kvm/vmx/main.c | 3 +-
arch/x86/kvm/vmx/nested.c | 84 +++++++++++++++++++++++---------------
arch/x86/kvm/vmx/vmx.c | 76 ++++++++++++++++++++--------------
arch/x86/kvm/vmx/vmx.h | 6 ++-
arch/x86/kvm/vmx/x86_ops.h | 3 +-
9 files changed, 120 insertions(+), 82 deletions(-)