This preparatory patch exposes the LED control bits in those Switch Config
Registers by mapping them at high addresses in the MIIM space, so the PHY
driver can access those registers and surely not collide with the existing
MIIM block registers. The two registers which are exposed are the global
Register 11 (0x0B): Global Control 9 as MIIM block register 0x0b00 and
port specific Register 29/45/61 (0x1D/0x2D/0x3D): Port 1/2/3 Control 10
as MIIM block register 0x0d00 . The access to those registers is further
restricted only to the LED configuration bits to prevent the PHY driver
or userspace tools like 'phytool' from tampering with any other switch
configuration through this interface.
I do wounder about using register numbers outside of the 0-31
range. We never have enforced it, but these clearly break 802.3 C22.
I wounder if it would be better to emulate pages as well. The PHYWhat would be the benefit of doing that, compared to the current approach? I think in either case, for example phytool could tamper with those registers anyway, right ?
driver already has lanphy_write_page_reg() and
lanphy_read_page_reg(). Could you emulate what those need? It adds a
lot of complexity, but it should be future proof.
What might be simpler is to expose an emulated C45 register range, and
put the registers in the vendor section.