Re: [PATCH v2 2/2] PCI: reread the Link Control 2 Register before using

[Jiwei]

On 1/18/25 09:03, Maciej W. Rozycki wrote:
> On Fri, 17 Jan 2025, Jiwei Sun wrote:
> 
>> However, within this section of code, lnkctl2 is not modified (after 
>> reading from register on line 111) at all and remains 0x5. This results 
>> in the condition on line 130 evaluating to 0 (false), which in turn 
>> prevents the code from line 132 onward from being executed. The removing
>> 2.5GT/s downstream link speed restriction work can not be done.
> 
>  It seems like a regression from my original code indeed.

Sorry, I am confused by this sentence.

IIUC, there is no regression regarding the lifting 2.5GT/s restriction in
the commit a89c82249c37 ("PCI: Work around PCIe link training failures").
However, since commit de9a6c8d5dbf ("PCI/bwctrl: Add 
pcie_set_target_speed() to set PCIe Link Speed"), the code to lift the 
restriction is no longer executed. Therefore, commit de9a6c8d5dbf 
("PCI/bwctrl: Add pcie_set_target_speed() to set PCIe Link Speed") can be
considered a regression of commit a a89c82249c37 ("PCI: Work around PCIe
link training failures").

So, this fix patch(PCI: reread the Link Control 2 Register before using) 
is required, right?

Thanks,
Regards,
Jiwei

> 
>   Maciej