Hey Marc, thanks for looking.
Marc Zyngier <maz@xxxxxxxxxx> writes:
On Mon, 27 Jan 2025 22:20:27 +0000,
Colton Lewis <coltonlewis@xxxxxxxxxx> wrote:
/* Read the nb of CNTx counters supported from PMNC */
- bitmap_set(cpu_pmu->cntr_mask,
- 0, FIELD_GET(ARMV8_PMU_PMCR_N, armv8pmu_pmcr_read()));
+ bitmap_set(cpu_pmu->cntr_mask, 0, pmcr_n);
+
+ if (reserved_guest_counters > 0 && reserved_guest_counters < pmcr_n) {
+ cpu_pmu->hpmn = reserved_guest_counters;
+ cpu_pmu->partitioned = true;
Isn't this going to completely explode on a kernel running at EL1?
Trying to access an EL2 register at EL1 can do that. I'll add the
appropriate hypercalls.
Also, how does it work in an asymmetric configuration where some CPUs
can satisfy the reservation, and some can't?
The CPUs that can't read their own value of PMCR.N below what the
attempted reservation is and so do not get partitioned. Nothing changes
for that CPU if it can't meet the reservation.