[PATCH RESEND] arm64: dts: mediatek: mt7622: readd syscon to pciesys node

[Daniel Golle]

From: Christian Marangi <ansuelsmth@xxxxxxxxx>

The sata node references the pciesys with the property
mediatek,phy-mode and that is used as a syscon to access the pciesys
registers.

Readd the syscon compatible to pciesys node to restore correct
functionality of the SATA interface.

Cc: stable@xxxxxxxxxxxxxxx
Co-developed-by: Frank Wunderlich <frank-w@xxxxxxxxxxxxxxx>
Fixes: 3ba5a6159434 ("arm64: dts: mediatek: mt7622: fix clock controllers")
Signed-off-by: Frank Wunderlich <frank-w@xxxxxxxxxxxxxxx>
Signed-off-by: Christian Marangi <ansuelsmth@xxxxxxxxx>
Signed-off-by: Daniel Golle <daniel@xxxxxxxxxxxxxx>
---
Note that the dt-bindings part of the original series has already been
applied with commit 9f7809c6a882 ("dt-bindings: clock: mediatek: add
syscon compatible for mt7622 pciesys").

 arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index e3421fd2c0ef..0710b8959ae8 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -790,7 +790,7 @@ u2port1: usb-phy@1a0c5000 {
 	};
 
 	pciesys: clock-controller@1a100800 {
-		compatible = "mediatek,mt7622-pciesys";
+		compatible = "mediatek,mt7622-pciesys", "syscon";
 		reg = <0 0x1a100800 0 0x1000>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
-- 
2.48.1