[tip: irq/core] dt-bindings: interrupt-controller: Add risc-v,aplic hart indexes

[tip-bot2 for Vladimir Kondratiev]

The following commit has been merged into the irq/core branch of tip:

Commit-ID:     c057b6e4213519e3ac167318238cd772b483f14a
Gitweb:        https://git.kernel.org/tip/c057b6e4213519e3ac167318238cd772b483f14a
Author:        Vladimir Kondratiev <vladimir.kondratiev@xxxxxxxxxxxx>
AuthorDate:    Wed, 29 Jan 2025 11:16:36 +02:00
Committer:     Thomas Gleixner <tglx@xxxxxxxxxxxxx>
CommitterDate: Mon, 03 Feb 2025 14:27:39 +01:00

dt-bindings: interrupt-controller: Add risc-v,aplic hart indexes

Document optional property "riscv,hart-indexes"

The RISC-V APLIC specification defines "hart index" in:

  https://github.com/riscv/riscv-aia

Within a given interrupt domain, each of the domain’s harts has a unique
index number in the range 0 to 2^14 − 1 (= 16,383). The index number a
domain associates with a hart may or may not have any relationship to the
unique hart identifier (“hart ID”) that the RISC-V Privileged Architecture
assigns to the hart. Two different interrupt domains may employ entirely
different index numbers for the same set of harts.

Further, this document says in "4.5 Memory-mapped control region for an
interrupt domain":

The array of IDC structures may include some for potential hart index
numbers that are not actual hart index numbers in the domain. For example,
the first IDC structure is always for hart index 0, but 0 is not
necessarily a valid index number for any hart in the domain.

Support arbitrary hart indexes specified in a optional APLIC property
"riscv,hart-indexes" which is specificed as an array of u32 elements, one
per interrupt target. If this property is not specified, fallback to use
the logical hart indices within the domain.

Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@xxxxxxxxxxxx>
Signed-off-by: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
Reviewed-by: Anup Patel <anup@xxxxxxxxxxxxxx>
Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
Link: https://lore.kernel.org/all/20250129091637.1667279-2-vladimir.kondratiev@xxxxxxxxxxxx
---
 Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
index 190a649..bef0052 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
@@ -91,6 +91,14 @@ properties:
       Firmware must configure interrupt delegation registers based on
       interrupt delegation list.
 
+  riscv,hart-indexes:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 1
+    maxItems: 16384
+    description:
+      A list of hart indexes that APLIC should use to address each hart
+      that is mentioned in the "interrupts-extended"
+
 dependencies:
   riscv,delegation: [ "riscv,children" ]