Re: [PATCH 0/3] Add support to reconfigure PLL

[Johan Hovold]

On Mon, Jan 13, 2025 at 10:57:03PM +0530, Taniya Das wrote:
> During boot-up, there is a possibility that the PLL configuration might
> be missed even after invoking pll_configure() from the clock controller
> probe. This is often due to the PLL being connected to rail or rails
> that are in an OFF state and current clock controller also cannot vote
> on multiple rails. As a result, the PLL may be enabled with suboptimal
> settings, leading to functional issues.
> 
> The PLL configuration, now part of clk_alpha_pll, can be reused to
> reconfigure the PLL to a known good state before scaling for frequency.
> The 'clk_alpha_pll_reconfigure()' can be updated to support more PLLs
> in future.

This sounds like a hack. You already describe the underlying problem (and
indirectly its solution) in the first paragraph above, namely that the
video clock controller has not enabled the power domain needed to
configure the PLL.

I believe support for clock controllers that need to enable multiple
power domains is on its way into 6.15:

	https://lore.kernel.org/lkml/20250117-b4-linux-next-24-11-18-clock-multiple-power-domains-v10-0-13f2bb656dad@xxxxxxxxxx/

Perhaps that's what you need to fix this properly.

> The IRIS driver support added
> https://lore.kernel.org/all/20241212-qcom-video-iris-v9-0-e8c2c6bd4041@xxxxxxxxxxx/
> observes the pll latch warning during boot up due to the dependency of
> the PLL not in good state, thus add config support for SM8550 Video
> clock controller PLLs.

> Taniya Das (3):
>       clk: qcom: clk-alpha-pll: Integrate PLL configuration into PLL structure
>       clk: qcom: clk-alpha-pll: Add support to reconfigure PLL
>       clk: qcom: videocc-sm8550: Update the pll config for Video PLLs

Johan