Re: [PATCH v3 01/10] irqchip/riscv-imsic: Handle non-atomic MSI updates for device

[Anup Patel]

On Tue, Feb 4, 2025 at 6:38 PM Thomas Gleixner <tglx@xxxxxxxxxxxxx> wrote:
>
> On Tue, Feb 04 2025 at 13:23, Anup Patel wrote:
> > Device having non-atomic MSI update might see an intermediate
> > state when changing target IMSIC vector from one CPU to another.
> >
> > To handle such intermediate device state, update MSI address
> > and MSI data through separate MSI writes to the device.
>
> As pointed out in the other mail, this intermediate step does not fix
> the issue. It requires that the MSI message write happens on the
> original target CPU so that an interrupt which is raised on that
> intermediate vector can be observed.

Okay, I will drop this patch and instead have the last patch do
the intermediate step.

Regards,
Anup