Re: [PATCH 2/2] drm/tidss: Add support for AM62L display subsystem

[Tomi Valkeinen]

Hi,

On 05/02/2025 07:53, Devarsh Thakkar wrote:
> Hi Tomi
>
> > > Thanks for pointing out, I probably missed this since the use-case still
> > > worked since VP interrupts were still enabled and those were sufficient to
> > > drive the display
> > > but the VID underflow interrupts and VID specific bits were probably not
> > > enabled at-all due to above miss, so agreed
> > > we should probably go ahead with a different reg space for AM62L due to
> > > aforementioned differences.
> >
> > I think I disagree here. Afaiu, AM62L has plane at hw index 1 (VIDL1), but the
> > plane at hw index 0 (VID1) is not instantiated in the hardware. But the
> > registers are the same, i.e. AM62L's registers for VIDL1 match AM65x/AM62x
> > registers, right?
> >
> > If so, we just need to tell the driver the hw index, instead of creating new
> > register offsets as done in v2.
> >
> > Or am I missing something here? (I haven't looked at the HW manual yet).
>
> No that's not the only difference. For AM62L, the VID_IRQENABLE/STATUS
> registers start at +0x4 as compared to AM65x/AM62x/ :
>
> AM62L:
>          [DISPC_VID_IRQENABLE_OFF] =             0x48,
>
>          [DISPC_VID_IRQSTATUS_OFF] =             0x5c,
>
> AM62x/AM65x:
>
>          [DISPC_VID_IRQENABLE_OFF] =             0x44,
>
>          [DISPC_VID_IRQSTATUS_OFF] =             0x58,

But they actually don't start at different offsets.

AM62L TRM has:

DSS_COMMON_VID_IRQENABLE_1  3020 0048h
DSS_COMMON_VID_IRQSTATUS_1  3020 005Ch

AM65X TRM has:

DSS0_COMMON_VID_IRQENABLE_1  04A0 0048h
DSS0_COMMON_VID_IRQSTATUS_1  04A0 005Ch

It's just that on AM62L the VID0 isn't instantiated in the hardware. 
VID1 is at the same place.

 Tomi