Re: [PATCH v5 08/16] cxl/pci: Map CXL PCIe Root Port and Downstream Switch Port RAS registers

[Bowman, Terry]

On 2/7/2025 1:30 AM, Gregory Price wrote:
> On Tue, Jan 07, 2025 at 08:38:44AM -0600, Terry Bowman wrote:
>> +static bool dev_is_cxl_pci(struct device *dev, u32 pcie_type)
>> +{
>> +	struct pci_dev *pdev;
>> +
>> +	if (!dev || !dev_is_pci(dev))
>> +		return false;
>> +
>> +	pdev = to_pci_dev(dev);
>> +
>> +	return (pci_pcie_type(pdev) == pcie_type);
>> +}
>> +
>> +static void cxl_init_ep_ports_aer(struct cxl_ep *ep)
>> +{
>> +	struct cxl_dport *dport = ep->dport;
>> +
>> +	if (dport) {
>> +		struct device *dport_dev = dport->dport_dev;
>> +
>> +		if (dev_is_cxl_pci(dport_dev, PCI_EXP_TYPE_DOWNSTREAM) ||
>> +		    dev_is_cxl_pci(dport_dev, PCI_EXP_TYPE_ROOT_PORT))
> Mostly an observation - this kind of comparison seems to be coming up
> more.  Wonder if an explicit set of APIs for these checks would be worth
> it to clean up the 3 or 4 different comparison variants i've seen.
>
> Either way
>
> Reviewed-by: Gregory Price <gourry@xxxxxxxxxx>
>
> ~Gregory
Do you recommend moving dev_is_cxl_pci() to pci library as is? Thanks for 'Reviewed-by:`. Terry