[PATCH v3 2/3] pwm: ehrpwm: add get_state function to retrieve PWM channel state

[Rafael V. Volkmer]

The ehrpwm driver was missing a get_state function, which is required
to properly retrieve the current state of the PWM channel. This commit
adds the ehrpwm_get_state() function, allowing users to query the
enabled state, period, duty cycle, and polarity of the PWM output.

The function reads the relevant registers (AQCSFRC, AQCTLx, TBPRD, CMPA)
to determine:
- Whether the PWM is enabled or disabled
- The configured period and duty cycle
- The polarity based on action-qualifier configurations

Additionally, this commit updates the pwm_ops structure to include
.get_state, ensuring proper integration with the PWM subsystem.

Signed-off-by: Rafael V. Volkmer <rafael.v.volkmer@xxxxxxxxx>
---
 drivers/pwm/pwm-tiehrpwm.c | 122 +++++++++++++++++++++++++++++++++++++
 1 file changed, 122 insertions(+)

diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c
index 50516f46ab04..52527136c507 100644
--- a/drivers/pwm/pwm-tiehrpwm.c
+++ b/drivers/pwm/pwm-tiehrpwm.c
@@ -81,7 +81,9 @@
 #define AQCTL_ZRO_MASK			GENMASK(1, 0)
 #define AQCTL_PRD_MASK			GENMASK(3, 2)
 #define AQCTL_CAU_MASK			GENMASK(5, 4)
+#define AQCTL_CAD_MASK			GENMASK(7, 6)
 #define AQCTL_CBU_MASK			GENMASK(9, 8)
+#define AQCTL_CBD_MASK			GENMASK(11, 10)
 
 /*
  * FORCE LOW	=> 0b01
@@ -495,9 +497,129 @@ static int ehrpwm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 	return err;
 }
 
+/**
+ * ehrpwm_get_state - Retrieves the current state of the eHRPWM channel
+ * @chip:	pointer to the PWM chip structure
+ * @pwm:	pointer to the PWM device structure
+ * @state:	pointer to the pwm_state structure to be filled
+ *
+ * @return:	0 on success or a negative error code on failure
+ */
+static int ehrpwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+							struct pwm_state *state)
+{
+	int ret = 0u;
+
+	struct ehrpwm_pwm_chip *pc = NULL;
+
+	unsigned long long tbclk_rate = 0u;
+
+	/* Registers */
+	u16 aqcsfrc_reg = 0u;
+	u16 aqctl_reg = 0u;
+	u16 tbprd_reg = 0u;
+	u16 cmpa_reg = 0u;
+
+	/* Bits */
+	u8 csf_bits = 0u;
+
+	/* Values */
+	u64 period_cycles = 0u;
+	u64 duty_cycles = 0u;
+
+	/* Actions */
+	u8 up_action = 0u;
+	u8 down_action = 0u;
+
+	if (chip == NULL || pwm == NULL || state == NULL)
+		return -EINVAL;
+
+	pc = to_ehrpwm_pwm_chip(chip);
+	if (pc == NULL || pwm == NULL || state == NULL)
+		return -EINVAL;
+
+	tbclk_rate = clk_get_rate(pc->tbclk);
+	if (tbclk_rate <= 0)
+		return -EINVAL;
+
+	/*< Get if EHRPWM is enable by checking registers values >*/
+
+	/*
+	 * The 'hwpwm' field identifies which hardware output channel (e.g.,
+	 * 0 for channel A and 1 for channel B) of the eHRPWM module is in use.
+	 */
+	if (pwm->hwpwm == 0) {
+		aqcsfrc_reg = readw(pc->mmio_base + AQCSFRC);
+		csf_bits = FIELD_GET(AQCSFRC_CSFA_MASK, aqcsfrc_reg);
+		aqctl_reg = readw(pc->mmio_base + AQCTLA);
+	} else {
+		aqcsfrc_reg = readw(pc->mmio_base + AQCSFRC);
+		csf_bits = FIELD_GET(AQCSFRC_CSFB_MASK, aqcsfrc_reg);
+		aqctl_reg = readw(pc->mmio_base + AQCTLB);
+	}
+
+	if (csf_bits)
+		state->enabled = false;
+
+	else if (aqctl_reg)
+		state->enabled = true;
+
+	/*< Get EHRPWM Period by checking registers values >*/
+	tbprd_reg = readw(pc->mmio_base + TBPRD);
+	period_cycles = (u64)(tbprd_reg + 1u);
+
+	/*
+	 * period (in ns) = (period_cycles * 1e9) / tbclk_rate
+	 * Using DIV_ROUND_UP_ULL to avoid floating-point operations.
+	 */
+	state->period = DIV_ROUND_UP_ULL(period_cycles * NSEC_PER_SEC, tbclk_rate);
+
+	/*< Get EHRPWM Duty Cycle by checking registers values >*/
+	cmpa_reg = readw(pc->mmio_base + CMPA);
+	duty_cycles = cmpa_reg;
+
+	/*
+	 * duty_cycle (in ns) = (duty_cycles * 1e9) / tbclk_rate
+	 * Using DIV_ROUND_UP_ULL to avoid floating-point operations.
+	 */
+	state->duty_cycle  = DIV_ROUND_UP_ULL(duty_cycles * NSEC_PER_SEC, tbclk_rate);
+
+	/*< Get EHRPWM polarity by checking registers values >*/
+
+	/*
+	 * The 'hwpwm' field identifies which hardware output channel (e.g.,
+	 * 0 for channel A and 1 for channel B) of the eHRPWM module is in use.
+	 */
+	if (pwm->hwpwm == 0) {
+		aqctl_reg = readw(pc->mmio_base + AQCTLA);
+		up_action = FIELD_GET(AQCTL_CAU_MASK, aqctl_reg);
+		down_action = FIELD_GET(AQCTL_CAD_MASK, aqctl_reg);
+	} else {
+		aqctl_reg = readw(pc->mmio_base + AQCTLB);
+		up_action = FIELD_GET(AQCTL_CBU_MASK, aqctl_reg);
+		down_action = FIELD_GET(AQCTL_CBD_MASK, aqctl_reg);
+	}
+
+	/*
+	 * Evaluate the actions to determine the PWM polarity:
+	 *  - If an up-count event sets the output (AQCTL_FRCHIGH) and a down-count
+	 *    event clears it (AQ_CLEAR), then polarity is NORMAL.
+	 *  - If an up-count event clears the output (AQ_CLEAR) and a down-count
+	 *    event sets it (AQCTL_FRCLOW), then polarity is INVERSED.
+	 */
+	if (up_action == AQCTL_FRCHIGH && down_action == AQCTL_FRCLOW)
+		state->polarity = PWM_POLARITY_NORMAL;
+
+	else if (up_action == AQCTL_FRCLOW && down_action == AQCTL_FRCHIGH)
+		state->polarity = PWM_POLARITY_INVERSED;
+
+	return ret;
+}
+
 static const struct pwm_ops ehrpwm_pwm_ops = {
 	.free = ehrpwm_pwm_free,
 	.apply = ehrpwm_pwm_apply,
+	.get_state = ehrpwm_get_state,
 };
 
 static const struct of_device_id ehrpwm_of_match[] = {
-- 
2.25.1