Re: [PATCH 2/3] arm64: dts: exynos: gs101: align reboot and poweroff writes with downstream
From: Peter Griffin
Date: Mon Feb 10 2025 - 01:23:51 EST
Hi André,
Thanks for your patch.
On Thu, 6 Feb 2025 at 13:08, André Draszik <andre.draszik@xxxxxxxxxx> wrote:
>
> For power off, downstream only clears bit 8 and leaves all other bits
> untouched, whereas this here ends up setting bit 8 and clearing all
> others, due to how sysconf-poweroff parses the DT.
That indeed sounds like a bug.
>
> For reboot, downstream writes 0x00000002 whereas this here ends up
> setting bit 1 only and leaving all others untouched.
For SYSTEM_CONFIGURATION register Bit[0] and bit[31:2] are reserved
and say "type R" (rather than RW for bit[1] so it seems correct to be
leaving the other bits untouched?
regards,
Peter
>
> I noticed this discrepancy while debugging some reboot related
> differences between up- and downstream and it's useful to align the
> behaviour here.
>
> Signed-off-by: André Draszik <andre.draszik@xxxxxxxxxx>
> ---
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index e78dcd506a5c..4f45bfeb33c0 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -1401,13 +1401,13 @@ pmu_system_controller: system-controller@17460000 {
> poweroff: syscon-poweroff {
> compatible = "syscon-poweroff";
> offset = <0x3e9c>; /* PAD_CTRL_PWR_HOLD */
> - mask = <0x100>; /* reset value */
> + mask = <0x00000100>;
> + value = <0x0>;
> };
>
> reboot: syscon-reboot {
> compatible = "syscon-reboot";
> offset = <0x3a00>; /* SYSTEM_CONFIGURATION */
> - mask = <0x2>; /* SWRESET_SYSTEM */
> value = <0x2>; /* reset value */
> };
> };
>
> --
> 2.48.1.362.g079036d154-goog
>