[PATCH 4/4] arm64: dts: qcom: qcs8300: Add support for stream 1 clk for DP MST

[Yongxing Mou]

Add 2 streams MST support for qcs8300. Compatile with qcs8300 dp
controller driver and populate the stream clock for qcs8300 DP0
controller in MST mode.

Signed-off-by: Yongxing Mou <quic_yongmou@xxxxxxxxxxx>
---
 arch/arm64/boot/dts/qcom/qcs8300.dtsi | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index e10db7275accf769500abbebf57a6cbbbc4bf167..5166686981617707ba19245723e9215a53300392 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -2865,12 +2865,13 @@ mdss_dp0_phy: phy@aec2a00 {
 		};
 
 		mdss_dp0: displayport-controller@af54000 {
-			compatible = "qcom,qcs8300-dp", "qcom,sm8650-dp";
+			compatible = "qcom,qcs8300-dp";
 
 			reg = <0x0 0x0af54000 0x0 0x200>,
 			      <0x0 0x0af54200 0x0 0x200>,
 			      <0x0 0x0af55000 0x0 0xc00>,
-			      <0x0 0x0af56000 0x0 0x400>;
+			      <0x0 0x0af56000 0x0 0x400>,
+			      <0x0 0x0af57000 0x0 0x400>;
 
 			interrupt-parent = <&mdss>;
 			interrupts = <12>;
@@ -2884,10 +2885,13 @@ mdss_dp0: displayport-controller@af54000 {
 				      "core_aux",
 				      "ctrl_link",
 				      "ctrl_link_iface",
-				      "stream_pixel";
+				      "stream_pixel",
+				      "stream_1_pixel";
 			assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
-					  <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+					  <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+					  <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
 			assigned-clock-parents = <&mdss_dp0_phy 0>,
+						 <&mdss_dp0_phy 1>,
 						 <&mdss_dp0_phy 1>;
 			phys = <&mdss_dp0_phy>;
 			phy-names = "dp";

-- 
2.34.1