Re: [PATCH v4 0/7] USB31DRD phy updates for Google Tensor gs101 (orientation & DWC3 rpm)

[Vinod Koul]

On Fri, 06 Dec 2024 16:31:00 +0000, André Draszik wrote:
> This series enables USB3 Type-C lane orientation detection and
> configuration on platforms that support this (Google gs101), and it
> also allows the DWC3 core to enter runtime suspend even when UDC is
> active.
> 
> For lane orientation, this driver now optionally (based on DT)
> subscribes to the TCPC's lane orientation notifier and remembers the
> orientation to later be used during phy_init().
> 
> [...]

Applied, thanks!

[1/7] dt-bindings: phy: samsung,usb3-drd-phy: add blank lines between DT properties
      commit: 642b1ed4cd184d5c2e5814c220bb93453492644d
[2/7] dt-bindings: phy: samsung,usb3-drd-phy: gs101: require Type-C properties
      commit: c38528812c2e9b05fe8b5fd1f66cf4c75835a38e
[3/7] phy: exynos5-usbdrd: convert to dev_err_probe
      commit: ee064390b82329df7fd8e0c48da03a8fee7d46ce
[4/7] phy: exynos5-usbdrd: fix EDS distribution tuning (gs101)
      commit: 21860f340ba76ee042e5431ff92537f89bc11476
[5/7] phy: exynos5-usbdrd: gs101: configure SS lanes based on orientation
      commit: 0bccdcb3eea93e087887027ff374dac5c3de36cd
[6/7] phy: exynos5-usbdrd: subscribe to orientation notifier if required
      commit: 09dc674295a388e71192430b6f9c3c5cb0eb47da
[7/7] phy: exynos5-usbdrd: allow DWC3 runtime suspend with UDC bound (E850+)
      commit: f4fb9c4d7f94dabef4abf2209cf840dd1c9ca11e

Best regards,
-- 
~Vinod