Re: [RFC PATCH 1/2] irqchip: ti-tsir: Add support for Timesync Interrupt Router

From: Chintan Vankar
Date: Sat Feb 15 2025 - 06:50:14 EST


Hello Thomas,

On 14/02/25 04:13, Thomas Gleixner wrote:
Chintan!

On Fri, Feb 14 2025 at 00:15, Vankar, Chintan wrote:
On 2/11/2025 1:33 AM, Thomas Gleixner wrote:
On Sun, Feb 09 2025 at 14:06, Vankar, Chintan wrote:
On 2/7/2025 2:58 AM, Thomas Gleixner wrote:
If I understand this correctly, then the interrupt number you need to
allocate for this is never going to be requested. If it would be
requested it just would do nothing and the handler would never be
invoked, right?

The allocation just establishes the routing of a signal between two
arbitrary IP blocks in the SoC.

So the question is what has this to do with interrupts in the first
place?

Your understanding is correct about the Timesync INTR. As I mentioned
Timesync INTR is an instance of Interrupt Router which has multiple
output and not all the output lines are acting as interrupt lines unlike
other Interrupt Routers. Timesync INTR can have devices on both the
sides, we can provide input to Timesync INTR that can be consumed by
some other device from the output line. As an instance, One of the
input of Timesync INTR is an output from the CPTS module which can be
consumed by other device and that does not need to handle/allocate Linux
irq number.

Two questions:

1) For the case where no interrupt is involved, how is the routing
configured?

2) For the case where it routes an input line to an interupt, then how
is this interrupt going to be handled by this interrupt domain which
is not connected to anything and implements an empty disfunctional
interrupt chip?


For both the cases above the job of Timesync INTR is to map the output
register with the corresponding input.

As described in section 11.3.2.1 in the TRM at:
https://www.ti.com/lit/ug/spruiu1d/spruiu1d.pdf,
the job of the Timesync INTR is to provide a configuration of the
"output registers which controls the selection". Hence we just have to
provide configuration APIs in the Timesync INTR which programs output
registers of the Timesync INTR. About the handling of the interrupts,
the device which receives an interrupt needs to handle the interrupt.

Could you please explain why we consider these two cases to be
different?


Regards,
Chintan.

Thanks

tglx