[PATCH v1 1/4] dt-bindings: phy: add samsung,exynos2200-snps-eusb2-phy schema file
From: Ivaylo Ivanov
Date: Sat Feb 15 2025 - 07:24:46 EST
The Exynos2200 SoC uses Synopsis eUSB2 PHY. Add a dt-binding schema
for the new driver.
Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@xxxxxxxxx>
---
.../samsung,exynos2200-snps-eusb2-phy.yaml | 75 +++++++++++++++++++
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/samsung,exynos2200-snps-eusb2-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/samsung,exynos2200-snps-eusb2-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,exynos2200-snps-eusb2-phy.yaml
new file mode 100644
index 000000000..d69a10f00
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung,exynos2200-snps-eusb2-phy.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/samsung,exynos2200-snps-eusb2-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SNPS eUSB2 phy controller
+
+maintainers:
+ - Ivaylo Ivanov <ivo.ivanov.ivanov1@xxxxxxxxx>
+
+description:
+ eUSB2 controller supports LS/FS/HS usb connectivity on Exynos chipsets.
+
+properties:
+ compatible:
+ enum:
+ - samsung,exynos2200-snps-eusb2-phy
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ clocks:
+ items:
+ - description: Reference clock
+ - description: APB clock
+ - description: Control PCLK
+
+ clock-names:
+ items:
+ - const: ref
+ - const: apb
+ - const: ctrl
+
+ phys:
+ maxItems: 1
+ description:
+ Phandle to USBCON phy
+
+ vdd-supply:
+ description:
+ Phandle to 0.88V regulator supply
+
+ vdda12-supply:
+ description:
+ Phandle to 1.2V regulator supply
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+ - clocks
+ - clock-names
+ - vdd-supply
+ - vdda12-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/samsung,exynos2200.h>
+
+ usb_hsphy: phy@10ab0000 {
+ compatible = "samsung,exynos2200-snps-eusb2-phy";
+ reg = <0 0x10ab0000 0 0x10000>;
+ clocks = <&cmu_hsi0 CLK_MOUT_HSI0_USB32DRD>,
+ <&cmu_hsi0 CLK_MOUT_HSI0_NOC>,
+ <&cmu_hsi0 CLK_DOUT_DIV_CLK_HSI0_EUSB>;
+ clock-names = "ref", "apb", "ctrl";
+ #phy-cells = <0>;
+ phys = <&usbcon_phy>;
+ };
--
2.43.0