[PATCH v1 3/4] phy: samsung: add Exynos2200 SNPS eUSB2 driver

[Ivaylo Ivanov]

The Exynos2200 SoC uses Synopsis eUSB2 PHY for USB 2.0. Add a new
driver for it.

eUSB2 on Exynos SoCs is usually paired alongside a USB PHY controller.
Currently the driver is modelled to take and enable/disable the usb phy
controller when needed.

The driver is based on information from downstream drivers.

Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@xxxxxxxxx>
---
 drivers/phy/samsung/Kconfig                   |  13 +
 drivers/phy/samsung/Makefile                  |   1 +
 .../phy/samsung/phy-exynos2200-snps-eusb2.c   | 351 ++++++++++++++++++
 3 files changed, 365 insertions(+)
 create mode 100644 drivers/phy/samsung/phy-exynos2200-snps-eusb2.c

diff --git a/drivers/phy/samsung/Kconfig b/drivers/phy/samsung/Kconfig
index e2330b089..f62285254 100644
--- a/drivers/phy/samsung/Kconfig
+++ b/drivers/phy/samsung/Kconfig
@@ -77,6 +77,19 @@ config PHY_S5PV210_USB2
 	  particular SoC is compiled in the driver. In case of S5PV210 two phys
 	  are available - device and host.
 
+config PHY_EXYNOS2200_SNPS_EUSB2
+	tristate "Exynos2200 eUSB 2.0 PHY driver"
+	depends on (ARCH_EXYNOS && OF) || COMPILE_TEST
+	depends on HAS_IOMEM
+	depends on USB_DWC3_EXYNOS
+	select GENERIC_PHY
+	select MFD_SYSCON
+	default y
+	help
+	  Enable USBCON PHY support for Exynos2200 SoC.
+	  This driver provides PHY interface for eUSB 2.0 controller
+	  present on Exynos5 SoC series.
+
 config PHY_EXYNOS5_USBDRD
 	tristate "Exynos5 SoC series USB DRD PHY driver"
 	depends on (ARCH_EXYNOS && OF) || COMPILE_TEST
diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
index fea1f96d0..90b84c7fc 100644
--- a/drivers/phy/samsung/Makefile
+++ b/drivers/phy/samsung/Makefile
@@ -14,5 +14,6 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2)	+= phy-exynos4210-usb2.o
 phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2)	+= phy-exynos4x12-usb2.o
 phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)	+= phy-exynos5250-usb2.o
 phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+= phy-s5pv210-usb2.o
+obj-$(CONFIG_PHY_EXYNOS2200_SNPS_EUSB2)	+= phy-exynos2200-snps-eusb2.o
 obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
 obj-$(CONFIG_PHY_EXYNOS5250_SATA)	+= phy-exynos5250-sata.o
diff --git a/drivers/phy/samsung/phy-exynos2200-snps-eusb2.c b/drivers/phy/samsung/phy-exynos2200-snps-eusb2.c
new file mode 100644
index 000000000..ee6d96411
--- /dev/null
+++ b/drivers/phy/samsung/phy-exynos2200-snps-eusb2.c
@@ -0,0 +1,351 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025, Ivaylo Ivanov <ivo.ivanov.ivanov1@xxxxxxxxx>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/iopoll.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mod_devicetable.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/reset.h>
+
+#define EXYNOS2200_EUSB2_RST_CTRL		0x0
+#define EXYNOS2200_UTMI_PORT_RESET_MASK		GENMASK(5, 4)
+#define EXYNOS2200_EUSB_PHY_RESET_MASK		GENMASK(1, 0)
+
+#define EXYNOS2200_EUSB2_CMN_CTRL		0x4
+#define EXYNOS2200_PHY_CFG_RPTR_MODE		BIT(10)
+#define EXYNOS2200_REF_FREQ_SEL			GENMASK(6, 4)
+#define EXYNOS2200_PHY_ENABLE			BIT(0)
+
+#define EXYNOS2200_EUSB2_PLLCFG0		0x8
+#define EXYNOS2200_PLL_FB_DIV_MASK		GENMASK(19, 8)
+
+#define EXYNOS2200_EUSB2_PLLCFG1		0xc
+#define EXYNOS2200_PLL_REF_DIV			GENMASK(11, 8)
+
+#define EXYNOS2200_EUSB2_TESTSE			0x20
+#define EXYNOS2200_TEST_IDDQ			BIT(6)
+
+struct exynos2200_snps_eusb2_phy_drvdata {
+	const char * const *clk_names;
+	int n_clks;
+	const char * const *regulator_names;
+	int n_regulators;
+};
+
+struct exynos2200_snps_eusb2_phy {
+	struct phy *phy;
+	void __iomem *base;
+
+	struct clk *ref_clk;
+	struct clk_bulk_data *clks;
+	const struct exynos2200_snps_eusb2_phy_drvdata *drv_data;
+	struct reset_control *phy_reset;
+
+	struct regulator_bulk_data *vregs;
+
+	enum phy_mode mode;
+
+	struct phy *repeater;
+	struct phy *usbcon;
+};
+
+static void exynos2200_snps_eusb2_phy_write_mask(void __iomem *base, u32 offset,
+						 u32 mask, u32 val)
+{
+	u32 reg;
+
+	reg = readl_relaxed(base + offset);
+	reg &= ~mask;
+	reg |= val & mask;
+	writel_relaxed(reg, base + offset);
+
+	/* ensure above write is completed */
+	readl_relaxed(base + offset);
+}
+
+static int exynos2200_snps_eusb2_ref_clk_init(struct exynos2200_snps_eusb2_phy *phy)
+{
+	unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk);
+
+	switch (ref_clk_freq) {
+	case 19200000:
+		exynos2200_snps_eusb2_phy_write_mask(phy->base, EXYNOS2200_EUSB2_CMN_CTRL,
+						     EXYNOS2200_REF_FREQ_SEL,
+						     0);
+
+		exynos2200_snps_eusb2_phy_write_mask(phy->base, EXYNOS2200_EUSB2_PLLCFG0,
+						     EXYNOS2200_PLL_FB_DIV_MASK,
+						     FIELD_PREP(EXYNOS2200_PLL_FB_DIV_MASK, 368));
+
+		exynos2200_snps_eusb2_phy_write_mask(phy->base, EXYNOS2200_EUSB2_PLLCFG1,
+						     EXYNOS2200_PLL_REF_DIV,
+						     FIELD_PREP(EXYNOS2200_PLL_FB_DIV_MASK, 0));
+		break;
+
+	case 20000000:
+		exynos2200_snps_eusb2_phy_write_mask(phy->base, EXYNOS2200_EUSB2_CMN_CTRL,
+						     EXYNOS2200_REF_FREQ_SEL,
+						     FIELD_PREP(EXYNOS2200_REF_FREQ_SEL, 1));
+
+		exynos2200_snps_eusb2_phy_write_mask(phy->base, EXYNOS2200_EUSB2_PLLCFG0,
+						     EXYNOS2200_PLL_FB_DIV_MASK,
+						     FIELD_PREP(EXYNOS2200_PLL_FB_DIV_MASK, 352));
+
+		exynos2200_snps_eusb2_phy_write_mask(phy->base, EXYNOS2200_EUSB2_PLLCFG1,
+						     EXYNOS2200_PLL_REF_DIV,
+						     FIELD_PREP(EXYNOS2200_PLL_FB_DIV_MASK, 0));
+		break;
+
+	case 24000000:
+		exynos2200_snps_eusb2_phy_write_mask(phy->base, EXYNOS2200_EUSB2_CMN_CTRL,
+						     EXYNOS2200_REF_FREQ_SEL,
+						     FIELD_PREP(EXYNOS2200_REF_FREQ_SEL, 2));
+
+		exynos2200_snps_eusb2_phy_write_mask(phy->base, EXYNOS2200_EUSB2_PLLCFG0,
+						     EXYNOS2200_PLL_FB_DIV_MASK,
+						     FIELD_PREP(EXYNOS2200_PLL_FB_DIV_MASK, 288));
+
+		exynos2200_snps_eusb2_phy_write_mask(phy->base, EXYNOS2200_EUSB2_PLLCFG1,
+						     EXYNOS2200_PLL_REF_DIV,
+						     FIELD_PREP(EXYNOS2200_PLL_FB_DIV_MASK, 0));
+		break;
+
+	case 26000000:
+		exynos2200_snps_eusb2_phy_write_mask(phy->base, EXYNOS2200_EUSB2_CMN_CTRL,
+						     EXYNOS2200_REF_FREQ_SEL,
+						     FIELD_PREP(EXYNOS2200_REF_FREQ_SEL, 3));
+
+		exynos2200_snps_eusb2_phy_write_mask(phy->base, EXYNOS2200_EUSB2_PLLCFG0,
+						     EXYNOS2200_PLL_FB_DIV_MASK,
+						     FIELD_PREP(EXYNOS2200_PLL_FB_DIV_MASK, 263));
+
+		exynos2200_snps_eusb2_phy_write_mask(phy->base, EXYNOS2200_EUSB2_PLLCFG1,
+						     EXYNOS2200_PLL_REF_DIV,
+						     FIELD_PREP(EXYNOS2200_PLL_FB_DIV_MASK, 0));
+		break;
+
+	case 48000000:
+		exynos2200_snps_eusb2_phy_write_mask(phy->base, EXYNOS2200_EUSB2_CMN_CTRL,
+						     EXYNOS2200_REF_FREQ_SEL,
+						     FIELD_PREP(EXYNOS2200_REF_FREQ_SEL, 2));
+
+		exynos2200_snps_eusb2_phy_write_mask(phy->base, EXYNOS2200_EUSB2_PLLCFG0,
+						     EXYNOS2200_PLL_FB_DIV_MASK,
+						     FIELD_PREP(EXYNOS2200_PLL_FB_DIV_MASK, 288));
+
+		exynos2200_snps_eusb2_phy_write_mask(phy->base, EXYNOS2200_EUSB2_PLLCFG1,
+						     EXYNOS2200_PLL_REF_DIV,
+						     FIELD_PREP(EXYNOS2200_PLL_FB_DIV_MASK, 1));
+		break;
+
+	default:
+		dev_err(&phy->phy->dev, "unsupported ref_clk_freq:%lu\n", ref_clk_freq);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int exynos2200_snps_eusb2_phy_init(struct phy *p)
+{
+	struct exynos2200_snps_eusb2_phy *phy = phy_get_drvdata(p);
+	int ret;
+
+	ret = regulator_bulk_enable(phy->drv_data->n_regulators, phy->vregs);
+	if (ret)
+		return ret;
+
+	ret = clk_bulk_prepare_enable(phy->drv_data->n_clks, phy->clks);
+	if (ret) {
+		dev_err(&p->dev, "failed to enable clocks, %d\n", ret);
+		goto disable_vreg;
+	}
+
+	ret = phy_init(phy->usbcon);
+	if (ret) {
+		dev_err(&p->dev, "usbcon init failed. %d\n", ret);
+		goto disable_ref_clk;
+	}
+
+	exynos2200_snps_eusb2_phy_write_mask(phy->base, EXYNOS2200_EUSB2_RST_CTRL,
+					     EXYNOS2200_UTMI_PORT_RESET_MASK |
+					     EXYNOS2200_EUSB_PHY_RESET_MASK,
+					     FIELD_PREP(EXYNOS2200_UTMI_PORT_RESET_MASK, 0x1) |
+					     FIELD_PREP(EXYNOS2200_EUSB_PHY_RESET_MASK, 0x1));
+	fsleep(50); /* required after holding phy in reset */
+
+	exynos2200_snps_eusb2_phy_write_mask(phy->base, EXYNOS2200_EUSB2_CMN_CTRL,
+					     EXYNOS2200_PHY_CFG_RPTR_MODE,
+					     EXYNOS2200_PHY_CFG_RPTR_MODE);
+
+	/* update ref_clk related registers */
+	ret = exynos2200_snps_eusb2_ref_clk_init(phy);
+	if (ret)
+		return ret;
+
+	exynos2200_snps_eusb2_phy_write_mask(phy->base, EXYNOS2200_EUSB2_TESTSE,
+					     EXYNOS2200_TEST_IDDQ,
+					     0);
+	fsleep(10); /* required after releasing test_iddq */
+
+	exynos2200_snps_eusb2_phy_write_mask(phy->base, EXYNOS2200_EUSB2_RST_CTRL,
+					     EXYNOS2200_EUSB_PHY_RESET_MASK,
+					     0);
+
+	exynos2200_snps_eusb2_phy_write_mask(phy->base, EXYNOS2200_EUSB2_CMN_CTRL,
+					     EXYNOS2200_PHY_ENABLE,
+					     EXYNOS2200_PHY_ENABLE);
+
+	exynos2200_snps_eusb2_phy_write_mask(phy->base, EXYNOS2200_EUSB2_RST_CTRL,
+					     EXYNOS2200_UTMI_PORT_RESET_MASK,
+					     0);
+	return 0;
+
+disable_ref_clk:
+	clk_disable_unprepare(phy->ref_clk);
+
+disable_vreg:
+	regulator_bulk_disable(phy->drv_data->n_regulators, phy->vregs);
+
+	return ret;
+}
+
+static int exynos2200_snps_eusb2_phy_exit(struct phy *p)
+{
+	struct exynos2200_snps_eusb2_phy *phy = phy_get_drvdata(p);
+
+	phy_exit(phy->usbcon);
+
+	clk_disable_unprepare(phy->ref_clk);
+	regulator_bulk_disable(phy->drv_data->n_regulators, phy->vregs);
+
+	return 0;
+}
+
+static const struct phy_ops exynos2200_snps_eusb2_phy_ops = {
+	.init		= exynos2200_snps_eusb2_phy_init,
+	.exit		= exynos2200_snps_eusb2_phy_exit,
+	.owner		= THIS_MODULE,
+};
+
+static int exynos2200_snps_eusb2_phy_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct exynos2200_snps_eusb2_phy *phy;
+	const struct exynos2200_snps_eusb2_phy_drvdata *drv_data;
+	struct phy_provider *phy_provider;
+	struct phy *generic_phy;
+	int ret;
+
+	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+	if (!phy)
+		return -ENOMEM;
+
+	drv_data = of_device_get_match_data(dev);
+	if (!drv_data)
+		return -EINVAL;
+	phy->drv_data = drv_data;
+
+	phy->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(phy->base))
+		return PTR_ERR(phy->base);
+
+	phy->clks = devm_kcalloc(dev, drv_data->n_clks,
+				 sizeof(*phy->clks), GFP_KERNEL);
+	if (!phy->clks)
+		return -ENOMEM;
+
+	for (int i = 0; i < drv_data->n_clks; ++i)
+		phy->clks[i].id = drv_data->clk_names[i];
+
+	ret = devm_clk_bulk_get(dev, drv_data->n_clks,
+				phy->clks);
+	if (ret)
+		return dev_err_probe(dev, ret,
+				     "failed to get phy clock(s)\n");
+
+	for (int i = 0; i < phy->drv_data->n_clks; ++i) {
+		if (!strcmp(phy->clks[i].id, "ref")) {
+			phy->ref_clk = phy->clks[i].clk;
+			break;
+		}
+	}
+
+	phy->vregs = devm_kcalloc(dev, drv_data->n_regulators,
+				  sizeof(*phy->vregs), GFP_KERNEL);
+	if (!phy->vregs)
+		return -ENOMEM;
+	regulator_bulk_set_supply_names(phy->vregs,
+					drv_data->regulator_names,
+					drv_data->n_regulators);
+	ret = devm_regulator_bulk_get(dev, drv_data->n_regulators,
+				      phy->vregs);
+	if (ret)
+		return dev_err_probe(dev, ret, "failed to get regulators\n");
+
+	/* we treat the usblink controller phy as a separate phy */
+	phy->usbcon = devm_of_phy_get_by_index(dev, np, 0);
+	if (IS_ERR(phy->usbcon))
+		return dev_err_probe(dev, PTR_ERR(phy->usbcon),
+				     "failed to get usbcon\n");
+
+	generic_phy = devm_phy_create(dev, NULL, &exynos2200_snps_eusb2_phy_ops);
+	if (IS_ERR(generic_phy)) {
+		dev_err(dev, "failed to create phy %d\n", ret);
+		return PTR_ERR(generic_phy);
+	}
+
+	dev_set_drvdata(dev, phy);
+	phy_set_drvdata(generic_phy, phy);
+
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+	if (IS_ERR(phy_provider)) {
+		dev_err(dev, "failed to register phy provider\n");
+		return PTR_ERR(phy_provider);
+	};
+
+	return 0;
+}
+
+static const char * const exynos2200_clk_names[] = {
+	"ref", "apb", "ctrl",
+};
+
+static const char * const exynos2200_regulator_names[] = {
+	"vdd", "vdda12",
+};
+
+static const struct exynos2200_snps_eusb2_phy_drvdata exynos2200_snps_eusb2_phy = {
+	.clk_names		= exynos2200_clk_names,
+	.n_clks			= ARRAY_SIZE(exynos2200_clk_names),
+	.regulator_names	= exynos2200_regulator_names,
+	.n_regulators		= ARRAY_SIZE(exynos2200_regulator_names),
+};
+
+static const struct of_device_id exynos2200_snps_eusb2_phy_of_match_table[] = {
+	{
+		.compatible = "samsung,exynos2200-snps-eusb2-phy",
+		.data = &exynos2200_snps_eusb2_phy,
+	}, { },
+};
+MODULE_DEVICE_TABLE(of, exynos2200_snps_eusb2_phy_of_match_table);
+
+static struct platform_driver exynos2200_snps_eusb2_phy_driver = {
+	.probe		= exynos2200_snps_eusb2_phy_probe,
+	.driver = {
+		.name	= "exynos2200-snps-eusb2-hsphy",
+		.of_match_table = exynos2200_snps_eusb2_phy_of_match_table,
+	},
+};
+
+module_platform_driver(exynos2200_snps_eusb2_phy_driver);
+MODULE_DESCRIPTION("Exynos2200 SNPS eUSB2 PHY driver");
+MODULE_LICENSE("GPL");
-- 
2.43.0