Re: [PATCH 3/3] i2c: qup: Vote for interconnect bandwidth to DRAM

From: Andi Shyti
Date: Tue Feb 18 2025 - 18:02:21 EST


Hi Stephen,

sorry for the very late reply here. Just one question.

...

> downstream/vendor driver [1]. Due to lack of documentation about the
> interconnect setup/behavior I cannot say exactly if this is right.
> Unfortunately, this is not implemented very consistently downstream...

Can we have someone from Qualcomm or Linaro taking a peak here?

> [1]: https://git.codelinaro.org/clo/la/kernel/msm-3.10/-/commit/67174e2624ea64814231e7e1e4af83fd882302c6

...

> @@ -1745,6 +1775,11 @@ static int qup_i2c_probe(struct platform_device *pdev)
> goto fail_dma;
> }
> qup->is_dma = true;
> +
> + qup->icc_path = devm_of_icc_get(&pdev->dev, NULL);
> + if (IS_ERR(qup->icc_path))
> + return dev_err_probe(&pdev->dev, PTR_ERR(qup->icc_path),
> + "failed to get interconnect path\n");

Can we live without it if it fails?

Thanks,
Andi