[tip: perf/core] perf amd ibs: Sync arch/x86/include/asm/amd-ibs.h header with the kernel

[tip-bot2 for Ravi Bangoria]

The following commit has been merged into the perf/core branch of tip:

Commit-ID:     3201bfa368fee5e70927e45222ff0b235352c01c
Gitweb:        https://git.kernel.org/tip/3201bfa368fee5e70927e45222ff0b235352c01c
Author:        Ravi Bangoria <ravi.bangoria@xxxxxxx>
AuthorDate:    Wed, 05 Feb 2025 06:05:43 
Committer:     Peter Zijlstra <peterz@xxxxxxxxxxxxx>
CommitterDate: Mon, 17 Feb 2025 15:20:05 +01:00

perf amd ibs: Sync arch/x86/include/asm/amd-ibs.h header with the kernel

Sync load latency related bit fields into the tool's header copy

Signed-off-by: Ravi Bangoria <ravi.bangoria@xxxxxxx>
Signed-off-by: Peter Zijlstra (Intel) <peterz@xxxxxxxxxxxxx>
Link: https://lkml.kernel.org/r/20250205060547.1337-4-ravi.bangoria@xxxxxxx
---
 tools/arch/x86/include/asm/amd-ibs.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/tools/arch/x86/include/asm/amd-ibs.h b/tools/arch/x86/include/asm/amd-ibs.h
index 93807b4..cb1740b 100644
--- a/tools/arch/x86/include/asm/amd-ibs.h
+++ b/tools/arch/x86/include/asm/amd-ibs.h
@@ -64,7 +64,8 @@ union ibs_op_ctl {
 			opmaxcnt_ext:7,	/* 20-26: upper 7 bits of periodic op maximum count */
 			reserved0:5,	/* 27-31: reserved */
 			opcurcnt:27,	/* 32-58: periodic op counter current count */
-			reserved1:5;	/* 59-63: reserved */
+			ldlat_thrsh:4,	/* 59-62: Load Latency threshold */
+			ldlat_en:1;	/* 63: Load Latency enabled */
 	};
 };