Re: [PATCH v4 1/9] dt-bindings: clock: rzv2h-cpg: Add syscon compatible for CPG

[Rob Herring (Arm)]

On Mon, 10 Feb 2025 18:49:02 +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> 
> The CPG block in the RZ/V2H(P) and RZ/G3E SoCs includes Error Reset Select
> Registers (`CPG_ERRORRST_SELm`) and Error Reset Registers
> (`CPG_ERROR_RSTm`). The `CPG_ERRORRST_SELm` register must be configured to
> trigger a system reset in response to specific error conditions, while the
> `CPG_ERROR_RSTm` registers store the error interrupt factors that caused
> the system reset. These registers can be used by various IP blocks as
> needed.
> 
> For example, in `CPG_ERRORRST_SEL2`, setting `BIT(1)` enables the WDT1 to
> issue a system reset upon a watchdog timer underflow. Similarly, `BIT(1)`
> in `CPG_ERROR_RST2` indicates whether the system reset was caused by a
> WDT1 underflow. This functionality allows the watchdog driver to configure
> the CPG_ERRORRST_SEL2 register and determine whether the system booted due
> to a `Power-on Reset` or a `Watchdog Reset`.
> 
> Add the `syscon` compatible property to the RZ/V2H(P) and RZ/G3E CPG
> blocks, enabling drivers to access the `CPG_ERRORRST_SELm` and
> `CPG_ERROR_RSTm` registers as needed.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> ---
> v3->v4
> - Updated commit meessage
> 
> v2->v3
> - No change
> 
> v1->v2
> - No change
> ---
>  .../devicetree/bindings/clock/renesas,rzv2h-cpg.yaml   | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
> 

Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>