Re: [PATCH v1 1/3] arm64: Add BBM Level 2 cpu feature
From: Yang Shi
Date: Wed Feb 19 2025 - 20:25:32 EST
On 2/19/25 6:38 AM, Mikołaj Lenczewski wrote:
The Break-Before-Make cpu feature supports multiple levels (levels 0-2),
and this commit adds a dedicated BBML2 cpufeature to test against
support for.
This is a system feature as we might have a big.LITTLE architecture
where some cores support BBML2 and some don't, but we want all cores to
be available and BBM to default to level 0 (as opposed to having cores
without BBML2 not coming online).
To support BBML2 in as wide a range of contexts as we can, we want not
only the architectural guarantees that BBML2 makes, but additionally
want BBML2 to not create TLB conflict aborts. Not causing aborts avoids
us having to prove that no recursive faults can be induced in any path
that uses BBML2, allowing its use for arbitrary kernel mappings.
Support detection of such CPUs.
Signed-off-by: Mikołaj Lenczewski <miko.lenczewski@xxxxxxx>
---
arch/arm64/Kconfig | 9 ++++++++
arch/arm64/include/asm/cpufeature.h | 5 +++++
arch/arm64/kernel/cpufeature.c | 32 +++++++++++++++++++++++++++++
arch/arm64/tools/cpucaps | 1 +
4 files changed, 47 insertions(+)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 940343beb3d4..84be2c5976f0 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -2057,6 +2057,15 @@ config ARM64_TLB_RANGE
The feature introduces new assembly instructions, and they were
support when binutils >= 2.30.
+config ARM64_ENABLE_BBML2
+ bool "Enable support for Break-Before-Make Level 2 detection and usage"
+ default y
+ help
+ FEAT_BBM provides detection of support levels for break-before-make
+ sequences. If BBM level 2 is supported, some TLB maintenance requirements
+ can be relaxed to improve performance. Selecting N causes the kernel to
+ fallback to BBM level 0 behaviour even if the system supports BBM level 2.
+
endmenu # "ARMv8.4 architectural features"
menu "ARMv8.5 architectural features"
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index e0e4478f5fb5..2da872035f2e 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -866,6 +866,11 @@ static __always_inline bool system_supports_mpam_hcr(void)
return alternative_has_cap_unlikely(ARM64_MPAM_HCR);
}
+static inline bool system_supports_bbml2_noconflict(void)
+{
+ return alternative_has_cap_unlikely(ARM64_HAS_BBML2_NOCONFLICT);
+}
+
int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt);
bool try_emulate_mrs(struct pt_regs *regs, u32 isn);
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index d561cf3b8ac7..8c337bd95ef7 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2176,6 +2176,31 @@ static bool hvhe_possible(const struct arm64_cpu_capabilities *entry,
return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE);
}
+static bool has_bbml2_noconflict(const struct arm64_cpu_capabilities *entry,
+ int scope)
+{
+ if (!IS_ENABLED(CONFIG_ARM64_ENABLE_BBML2))
+ return false;
+
+ /* We want to allow usage of bbml2 in as wide a range of kernel contexts
+ * as possible. This list is therefore an allow-list of known-good
+ * implementations that both support bbml2 and additionally, fulfil the
+ * extra constraint of never generating TLB conflict aborts when using
+ * the relaxed bbml2 semantics (such aborts make use of bbml2 in certain
+ * kernel contexts difficult to prove safe against recursive aborts).
+ */
+ static const struct midr_range supports_bbml2_without_abort_list[] = {
+ MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf),
+ MIDR_REV_RANGE(MIDR_NEOVERSE_V3, 0, 2, 0xf),
+ {}
+ };
+
+ if (!is_midr_in_range_list(read_cpuid_id(), supports_bbml2_without_abort_list))
+ return false;
+
+ return true;
+}
+
#ifdef CONFIG_ARM64_PAN
static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
{
@@ -2926,6 +2951,13 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.matches = has_cpuid_feature,
ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP)
},
+ {
+ .desc = "BBM Level 2 without conflict abort",
+ .capability = ARM64_HAS_BBML2_NOCONFLICT,
+ .type = ARM64_CPUCAP_SYSTEM_FEATURE,
+ .matches = has_bbml2_noconflict,
+ ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, BBM, 2)
Hi Miko,
Thanks for cc'ing me this series. I and Ryan discussed about how to
advertise BBML2 properly in my thread
(https://lore.kernel.org/linux-arm-kernel/4c44cf6e-98de-47bb-b430-2b1331114904@xxxxxxxxxxxxxxxxxxxxxx/).
IIUC, this may not work as expected.
The boot cpu initializes the boot_cpu_data, then the secondary cpus need
to update it, the "sanitized" register value will be generated. For
example, TLB range capability is determined by ISAR0_EL1. If all the
cpus have this feature, the "sanitized" register value will show true
otherwise it will show false.
BBML2 can be determined by MMFR2_EL1. If we can rely on it then system
feature does work. But the problem is some implementations may have
MMFR2_EL1 set, but they may not be able to handle TLB conflict. We can't
rely on it solely so we check MIDR in .matches callback instead of
MMFR2_EL1. But system feature .matches callback is just called once on
boot CPU because it is supposed to read the sanitized register value. So
you actually just checked the MIDR on boot CPU in .matches callback if I
read the code correctly.
I'm not quite familiar with cpufeature details, if I'm wrong please feel
free to correct me.
Yang
+ },
{
.desc = "52-bit Virtual Addressing for KVM (LPA2)",
.capability = ARM64_HAS_LPA2,
diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
index 1e65f2fb45bd..8d67bb4448c5 100644
--- a/arch/arm64/tools/cpucaps
+++ b/arch/arm64/tools/cpucaps
@@ -26,6 +26,7 @@ HAS_ECV
HAS_ECV_CNTPOFF
HAS_EPAN
HAS_EVT
+HAS_BBML2_NOCONFLICT
HAS_FPMR
HAS_FGT
HAS_FPSIMD