Re: [PATCH v5 5/5] x86/cpufeatures: Add the CPU feature bit for MSR immediate form instructions

[Borislav Petkov]

On Sun, Jan 05, 2025 at 11:07:27PM -0800, Xin Li (Intel) wrote:
> The immediate form of MSR access instructions are primarily motivated by
> performance, not code size: by having the MSR number in an immediate, it
> is available *much* earlier in the pipeline, which allows the hardware
> much more leeway about how a particular MSR is handled.
> 
> Add a new CPU feature word for CPUID.7.1.ECX and then the CPU feature bit
> for MSR immediate form.

Nope, scattered.c.

> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index d5985e8eef29..59aa04915032 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -5,7 +5,7 @@
>  /*
>   * Defines x86 CPU feature bits
>   */
> -#define NCAPINTS			22	   /* N 32-bit words worth of info */
> +#define NCAPINTS			23	   /* N 32-bit words worth of info */
>  #define NBUGINTS			2	   /* N 32-bit bug flags */
>  
>  /*
> @@ -476,6 +476,9 @@
>  #define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core Topology */
>  #define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32 + 7) /* Workload Classification */
>  
> +/* Intel-defined CPU features, CPUID level 0x00000007:1 (ECX), word 22 */
> +#define X86_FEATURE_MSR_IMM		(22*32+ 5) /* "msr_imm" MSR immediate form instructions */

Also no "msr_imm": Documentation/arch/x86/cpuinfo.rst

In any case, this patch doesn't belong in this set.

Thx.

-- 
Regards/Gruss,
    Boris.

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