Re: [PATCH v3 5/8] phy: rockchip: samsung-hdptx: Setup TMDS char rate via phy_configure_opts_hdmi
From: Dmitry Baryshkov
Date: Sun Feb 23 2025 - 18:38:52 EST
On Sun, 23 Feb 2025 at 13:02, Cristian Ciocaltea
<cristian.ciocaltea@xxxxxxxxxxxxx> wrote:
>
> The current workaround to setup the TMDS character rate relies on the
> unconventional usage of phy_set_bus_width().
>
> Make use of the recently introduced HDMI PHY configuration API for this
> purpose. The workaround will be dropped as soon as the switch has been
> completed on both ends.
>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@xxxxxxxxxxxxx>
> ---
> drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 37 +++++++++++++++++------
> 1 file changed, 27 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> index f9b5c96d6c789e435657e224032d35b5a6950945..dd91a7272e246b2133112effdb080a847fd15abe 100644
> --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> @@ -402,6 +402,9 @@ struct rk_hdptx_phy {
> int nr_clks;
> struct reset_control_bulk_data rsts[RST_MAX];
>
> + /* PHY config opts */
> + unsigned long tmds_char_rate;
It's easier to embed struct phy_configure_opts_hdmi here, in the end
you add bpc here in one of the next patches.
> +
> /* clk provider */
> struct clk_hw hw;
> unsigned long rate;
> @@ -1413,19 +1416,21 @@ static int rk_hdptx_dp_aux_init(struct rk_hdptx_phy *hdptx)
> static int rk_hdptx_phy_power_on(struct phy *phy)
> {
> struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
> - int bus_width = phy_get_bus_width(hdptx->phy);
> + unsigned int rate = hdptx->tmds_char_rate / 100;
> enum phy_mode mode = phy_get_mode(phy);
> int ret, lane;
>
> - /*
> - * FIXME: Temporary workaround to pass pixel_clk_rate
> - * from the HDMI bridge driver until phy_configure_opts_hdmi
> - * becomes available in the PHY API.
> - */
> - unsigned int rate = bus_width & 0xfffffff;
> + if (rate == 0) {
> + /*
> + * FIXME: Temporary workaround to setup TMDS char rate
> + * from the RK HDMI bridge driver.
> + * Will be removed as soon the switch to the HDMI PHY
> + * configuration API has been completed on both ends.
> + */
> + rate = phy_get_bus_width(hdptx->phy) & 0xfffffff;
> + }
>
> - dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n",
> - __func__, bus_width, rate);
> + dev_dbg(hdptx->dev, "%s rate=%u\n", __func__, rate);
>
> ret = rk_hdptx_phy_consumer_get(hdptx, rate);
> if (ret)
> @@ -1734,8 +1739,10 @@ static int rk_hdptx_phy_configure(struct phy *phy, union phy_configure_opts *opt
> enum phy_mode mode = phy_get_mode(phy);
> int ret;
>
> - if (mode != PHY_MODE_DP)
> + if (mode != PHY_MODE_DP) {
> + hdptx->tmds_char_rate = opts->hdmi.tmds_char_rate;
> return 0;
> + }
>
> ret = rk_hdptx_phy_verify_config(hdptx, &opts->dp);
> if (ret) {
> @@ -1830,6 +1837,16 @@ static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
> {
> struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
>
> + /*
> + * The TMDS char rate set via phy_configure(), if any, has
> + * precedence over the rate provided via clk_set_rate().
I think this is not so nice. It makes CCF desync from the actual rate
programmed into the hardware. Maybe you can make the clock r/o?
> + */
> + if (hdptx->tmds_char_rate && hdptx->tmds_char_rate != rate) {
> + dev_dbg(hdptx->dev, "Replaced clk_set_rate=%lu with tmds_char_rate=%lu\n",
> + rate, hdptx->tmds_char_rate);
> + rate = hdptx->tmds_char_rate;
> + }
> +
> return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate / 100);
> }
>
>
> --
> 2.48.1
>
--
With best wishes
Dmitry