Re: [Patch v2 10/24] perf/x86/intel: Process arch-PEBS records or record fragments

[Mi, Dapeng]

On 2/25/2025 6:39 PM, Peter Zijlstra wrote:
> On Tue, Feb 18, 2025 at 03:28:04PM +0000, Dapeng Mi wrote:
>> A significant difference with adaptive PEBS is that arch-PEBS record
>> supports fragments which means an arch-PEBS record could be split into
>> several independent fragments which have its own arch-PEBS header in
>> each fragment.
>>
>> This patch defines architectural PEBS record layout structures and add
>> helpers to process arch-PEBS records or fragments. Only legacy PEBS
>> groups like basic, GPR, XMM and LBR groups are supported in this patch,
>> the new added YMM/ZMM/OPMASK vector registers capturing would be
>> supported in subsequent patches.
>>
>> Signed-off-by: Dapeng Mi <dapeng1.mi@xxxxxxxxxxxxxxx>
>> ---
>>  arch/x86/events/intel/core.c      |   9 ++
>>  arch/x86/events/intel/ds.c        | 219 ++++++++++++++++++++++++++++++
>>  arch/x86/include/asm/msr-index.h  |   6 +
>>  arch/x86/include/asm/perf_event.h | 100 ++++++++++++++
>>  4 files changed, 334 insertions(+)
>>
>> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
>> index 37540eb80029..184f69afde08 100644
>> --- a/arch/x86/events/intel/core.c
>> +++ b/arch/x86/events/intel/core.c
>> @@ -3124,6 +3124,15 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status)
>>  			wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
>>  	}
>>  
>> +	/*
>> +	 * Arch PEBS sets bit 54 in the global status register
>> +	 */
>> +	if (__test_and_clear_bit(GLOBAL_STATUS_ARCH_PEBS_THRESHOLD_BIT,
>> +				 (unsigned long *)&status)) {
> Will arch_pebs hardware ever toggle bit 62?

No, arch-PEBS won't touch anything of debug store related.


>
>> +		handled++;
>> +		x86_pmu.drain_pebs(regs, &data);
> 		static_call(x86_pmu_drain_pebs)(regs, &data);

Sure.


>
>> +	}
>