Re: [PATCH] riscv: select DMA_DIRECT_REMAP by RISCV_ISA_SVPBMT and ERRATA_THEAD_MAE

From: Alexandre Ghiti
Date: Wed Feb 26 2025 - 08:59:11 EST

+cc Marek

On 20/02/2025 10:48, Sergey Matyukevich wrote:
Hi Alexandre,

On Mon, Feb 17, 2025 at 01:23:28PM +0100, Alexandre Ghiti wrote:
Hi Sergey,

On 16/01/2025 18:29, Sergey Matyukevich wrote:
Select DMA_DIRECT_REMAP for the RISC-V extensions that allow to set
page-based memory types in PTEs according to the requested DMA
attributes. This is the purpose of Svpbmt or XTheadMae extensions.
Zicbom or XTheadCmo serve a different purpose, providing instructions
to flush/invalidate cache blocks.

Fixes: 381cae169853 ("riscv: only select DMA_DIRECT_REMAP from RISCV_ISA_ZICBOM and ERRATA_THEAD_PBMT")

Signed-off-by: Sergey Matyukevich <geomatsi@xxxxxxxxx>
---
arch/riscv/Kconfig | 2 +-
arch/riscv/Kconfig.errata | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index d4a7ca0388c0..a5dabb744009 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -603,6 +603,7 @@ config RISCV_ISA_SVPBMT
depends on 64BIT && MMU
depends on RISCV_ALTERNATIVE
default y
+ select DMA_DIRECT_REMAP

From what I read, DMA_DIRECT_MAP relies on the ability to map pages uncached
(pgprot_dmacoherent() here
https://elixir.bootlin.com/linux/v6.13.2/source/kernel/dma/pool.c#L104). But
CONFIG_RISCV_ISA_SVPBMT does not guarantee that the underlying platform
supports svpbmt so to me it is wrong to select DMA_DIRECT_MAP, we would need
some runtime check instead.
IIUC this function highlights coherent dma allocation options and their
requirements even more clearly:
- https://elixir.bootlin.com/linux/v6.13.2/source/kernel/dma/direct.c#L222

help
Adds support to dynamically detect the presence of the Svpbmt
ISA-extension (Supervisor-mode: page-based memory types) and
@@ -787,7 +788,6 @@ config RISCV_ISA_ZICBOM
depends on RISCV_ALTERNATIVE
default y
select RISCV_DMA_NONCOHERENT

And in the same way, we should not enable RISCV_DMA_NONCOHERENT since
CONFIG_RISCV_ISA_ZICBOM does guarantee the presence of zicbom. Because then
in mm/dma-noncoherent.c, the cache flush operations are nops.

Or am I missing something?
This is my understanding as well. In fact this patch is almost useless.
It would only allow to enable DMA_GLOBAL_POOL for platforms that support
Zicbom, but do not support Svpbmt.

The actual problem is that the RISC-V kernel image cannot have both
DMA_DIRECT_REMAP and DMA_GLOBAL_POOL since they are now mutually
exclusive in kernel/dma/Kconfig. This limitation is not convenient for
RISC-V, where kernels can be built with support for multiple extensions
and errata. But on boot only appropriate subset of them is enabled based
on the chip's VENDOR_ID and selected dtb.

Currently a portable RISC-V kernel is suitable only for platforms with
support for both Zicbom and Svpbmt or their vendor-specific alternatives.
So it doesn't really matter where DMA_DIRECT_REMAP is selected. Platforms
without Svpbmt need to build their own non-portable kernels anyway,
enabling support for DMA_GLOBAL_POOL. For instance, Starfive and Andes
in arch/riscv/Kconfig.errata and drivers/soc/renesas/Kconfig respectively.

Maybe one possible option would be to revert commit da323d464070
("dma-direct: add dependencies to CONFIG_DMA_GLOBAL_POOL") and add runtime
checks in dma_direct_alloc for dma_alloc_from_global_coherent.


And dma_common_contiguous_remap(). Others? I guess the best would be to have a patch to propose, unless Christoph or Marek answer with ideas.

Can you prepare something Sergey?

Thanks,

Alex



In that case RISC-V kernels could be built with support for both
DMA_GLOBAL_POOL and DMA_DIRECT_REMAP. Global pool code path could be
enabled only for platforms that explicitly specify it in their dtbs.

Regards,
Sergey

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