Re: [PATCH RFC v1 02/11] x86/fpu/xstate: Introduce xstate order table and accessor macro

[Ingo Molnar]

* Ingo Molnar <mingo@xxxxxxxxxx> wrote:

> 
> * Andrew Cooper <andrew.cooper3@xxxxxxxxxx> wrote:
> 
> > > There's no incompatibility for a default-disabled feature that gets 
> > > enabled by an AVX-aware host kernel and by AVX-aware guest kernels. 
> > > What ABI would be broken?
> > 
> > I don't understand your question.
> >
> > XSAVE, and details about in CPUID, are a stated ABI (given in the SDM 
> > and APM), and available in userspace, including for userpace to write 
> > into a file/socket and interpret later (this is literally how we 
> > migrate VMs between different hosts).
> > 
> > You simply redefine what %xcr0.bnd_* (a.k.a. XFEATURES 3 and 4) mean, 
> > irrespective of what a guest kernel thinks it can get away with.
> 
> XFEATURES bits 3 and 4 are zero by default in the CPU, so the previous 
> ABI promise has been fully met: MPX is unavailable and disabled.
> 
> I propose a new addition, an extension of functionality: if a new CPUID 
> bit indicates it, and a new MSR is written, XFEATURES bit 3 becomes 
> active again - and the MPX area is now used by AVX. Obviously only 
> AVX-aware host and guest kernels would enable AVX.

Erm, s/AVX/APX ...

Too many acronyms.

Thanks,

	Ingo