Re: [PATCH RFC v1 02/11] x86/fpu/xstate: Introduce xstate order table and accessor macro

[Chang S. Bae]

On 2/27/2025 1:30 PM, Ingo Molnar wrote:
> * Ingo Molnar <mingo@xxxxxxxxxx> wrote:
> > I propose a new addition, an extension of functionality: if a new CPUID
> > bit indicates it, and a new MSR is written, XFEATURES bit 3 becomes
> > active again - and the MPX area is now used by AVX. Obviously only
> > AVX-aware host and guest kernels would enable AVX.
>
> Erm, s/AVX/APX ...

Just thought of another aspect of this:

I'm curious about how core dumps should handle this. Initially, an 
xfeature mask was added to the software-reserved area [1] to indicate 
which xfeatures were present in the layout. More recently, a new note 
[2] was introduced to expose CPUID-reported size and offset information, 
helping tools like GDB. From an offline interpretation standpoint, I 
think these bits will become ambiguous without further extensions.

[1] commit 5b3efd500854 ("x86, ptrace: regset extensions to support xstate")
[2] commit ba386777a30b ("x86/elf: Add a new FPU buffer layout info to 
x86 core files")

Thanks,
Chang