Re: [PATCH] genirq/msi: Add the address and data that show MSI/MSIX

From: Hans Zhang
Date: Fri Feb 28 2025 - 04:05:36 EST

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In reply to: Thomas Gleixner: "Re: [PATCH] genirq/msi: Add the address and data that show MSI/MSIX"
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On 2025/2/28 01:51, Thomas Gleixner wrote:

On Thu, Feb 27 2025 at 22:09, Manivannan Sadhasivam wrote:

On Fri, Feb 28, 2025 at 12:28:21AM +0800, Hans Zhang wrote:

+ return sysfs_emit(
+ buf,
+ "%s\n address_hi: 0x%08x\n address_lo: 0x%08x\n msg_data: 0x%08x\n",
+ is_msix ? "msix" : "msi", desc->msg.address_hi,
+ desc->msg.address_lo, desc->msg.data);

Sysfs is an ABI. You cannot change the semantics of an attribute.

Correct. Aside of that this is debug information and has no business in
sysfs.

The obvious place to expose this is via the existing debugfs irq/*
mechanism. All it requires is to implement a debug_show() callback in
the MSI core code and assign it to domain ops::debug_show() on domain
creation, if it does not provide its own callback.

Hi Thomas(tglx),

Is the following patch OK? Please give me some advice. Thank you very much.

Best regards
Hans

patch:

diff --git a/kernel/irq/debugfs.c b/kernel/irq/debugfs.c
index ca142b9a4db3..447fa24520f4 100644
--- a/kernel/irq/debugfs.c
+++ b/kernel/irq/debugfs.c
@@ -3,6 +3,7 @@

#include <linux/irqdomain.h>
#include <linux/irq.h>
+#include <linux/msi.h>
#include <linux/uaccess.h>

#include "internals.h"
@@ -56,6 +57,26 @@ static const struct irq_bit_descr irqchip_flags[] = {
BIT_MASK_DESCR(IRQCHIP_MOVE_DEFERRED),
};

+static void irq_debug_show_msi_msix(struct seq_file *m, struct irq_data *data,
+ int ind)
+{
+ struct msi_desc *desc;
+ bool is_msix;
+
+ desc = irq_get_msi_desc(data->irq);
+ if (!desc)
+ return;
+
+ is_msix = desc->pci.msi_attrib.is_msix;
+ seq_printf(m, "%*s%s:", ind, "", is_msix ? "msix" : "msi");
+ seq_printf(m, "\n%*saddress_hi: 0x%08x", ind + 1, "",
+ desc->msg.address_hi);
+ seq_printf(m, "\n%*saddress_lo: 0x%08x", ind + 1, "",
+ desc->msg.address_lo);
+ seq_printf(m, "\n%*smsg_data: 0x%08x\n", ind + 1, "",
+ desc->msg.data);
+}
+
static void
irq_debug_show_chip(struct seq_file *m, struct irq_data *data, int ind)
{
@@ -178,6 +199,7 @@ static int irq_debug_show(struct seq_file *m, void *p)
seq_printf(m, "node: %d\n", irq_data_get_node(data));
irq_debug_show_masks(m, desc);
irq_debug_show_data(m, data, 0);
+ irq_debug_show_msi_msix(m, data, 0);
raw_spin_unlock_irq(&desc->lock);
return 0;
}

e.g.
root@root:/sys/kernel/debug/irq/irqs# cat /proc/interrupts | grep ITS
85: 0 0 0 0 0 0 0 0 0 0 0 0 ITS-MSI 75497472 Edge PCIe PME, aerdrv
86: 0 30 0 0 0 0 0 0 0 0 0 0 ITS-MSI 76021760 Edge nvme0q0
87: 682 0 0 0 0 0 0 0 0 0 0 0 ITS-MSI 76021761 Edge nvme0q1
88: 0 400 0 0 0 0 0 0 0 0 0 0 ITS-MSI 76021762 Edge nvme0q2
89: 0 0 246 0 0 0 0 0 0 0 0 0 ITS-MSI 76021763 Edge nvme0q3
90: 0 0 0 141 0 0 0 0 0 0 0 0 ITS-MSI 76021764 Edge nvme0q4
91: 0 0 0 0 177 0 0 0 0 0 0 0 ITS-MSI 76021765 Edge nvme0q5
92: 0 0 0 0 0 173 0 0 0 0 0 0 ITS-MSI 76021766 Edge nvme0q6
93: 0 0 0 0 0 0 374 0 0 0 0 0 ITS-MSI 76021767 Edge nvme0q7
94: 0 0 0 0 0 0 0 62 0 0 0 0 ITS-MSI 76021768 Edge nvme0q8
95: 0 0 0 0 0 0 0 0 137 0 0 0 ITS-MSI 76021769 Edge nvme0q9
96: 0 0 0 0 0 0 0 0 0 177 0 0 ITS-MSI 76021770 Edge nvme0q10
97: 0 0 0 0 0 0 0 0 0 0 403 0 ITS-MSI 76021771 Edge nvme0q11
98: 0 0 0 0 0 0 0 0 0 0 0 246 ITS-MSI 76021772 Edge nvme0q12
root@root:/sys/kernel/debug/irq/irqs# cat 86
handler: handle_fasteoi_irq
device: 0000:91:00.0
status: 0x00000000
istate: 0x00004000
ddepth: 0
wdepth: 0
dstate: 0x31401200
IRQD_ACTIVATED
IRQD_IRQ_STARTED
IRQD_SINGLE_TARGET
IRQD_AFFINITY_SET
IRQD_AFFINITY_ON_ACTIVATE
IRQD_HANDLE_ENFORCE_IRQCTX
node: 0
affinity: 6
effectiv: 6
domain: :soc@0:interrupt-controller@0e001000:its@0e050000-3
hwirq: 0x4880000
chip: ITS-MSI
flags: 0x20
IRQCHIP_ONESHOT_SAFE
parent:
domain: :soc@0:interrupt-controller@0e001000:its@0e050000-5
hwirq: 0x2001
chip: ITS
flags: 0x0
parent:
domain: :soc@0:interrupt-controller@0e001000-1
hwirq: 0x2001
chip: GICv3
flags: 0x15
IRQCHIP_SET_TYPE_MASKED
IRQCHIP_MASK_ON_SUSPEND
IRQCHIP_SKIP_SET_WAKE
msix:
address_hi: 0x00000000
address_lo: 0x0e060040
msg_data: 0x00000000
root@root:/sys/kernel/debug/irq/irqs# cat 87
handler: handle_fasteoi_irq
device: 0000:91:00.0
status: 0x00000000
istate: 0x00004000
ddepth: 0
wdepth: 0
dstate: 0x31600200
IRQD_ACTIVATED
IRQD_IRQ_STARTED
IRQD_SINGLE_TARGET
IRQD_AFFINITY_MANAGED
IRQD_AFFINITY_ON_ACTIVATE
IRQD_HANDLE_ENFORCE_IRQCTX
node: 0
affinity: 0
effectiv: 0
domain: :soc@0:interrupt-controller@0e001000:its@0e050000-3
hwirq: 0x4880001
chip: ITS-MSI
flags: 0x20
IRQCHIP_ONESHOT_SAFE
parent:
domain: :soc@0:interrupt-controller@0e001000:its@0e050000-5
hwirq: 0x2002
chip: ITS
flags: 0x0
parent:
domain: :soc@0:interrupt-controller@0e001000-1
hwirq: 0x2002
chip: GICv3
flags: 0x15
IRQCHIP_SET_TYPE_MASKED
IRQCHIP_MASK_ON_SUSPEND
IRQCHIP_SKIP_SET_WAKE
msix:
address_hi: 0x00000000
address_lo: 0x0e060040
msg_data: 0x00000001
root@root:/sys/kernel/debug/irq/irqs#
root@root:/sys/kernel/debug/irq/irqs# cat 88
handler: handle_fasteoi_irq
device: 0000:91:00.0
status: 0x00000000
istate: 0x00004000
ddepth: 0
wdepth: 0
dstate: 0x31600200
IRQD_ACTIVATED
IRQD_IRQ_STARTED
IRQD_SINGLE_TARGET
IRQD_AFFINITY_MANAGED
IRQD_AFFINITY_ON_ACTIVATE
IRQD_HANDLE_ENFORCE_IRQCTX
node: 0
affinity: 1
effectiv: 1
domain: :soc@0:interrupt-controller@0e001000:its@0e050000-3
hwirq: 0x4880002
chip: ITS-MSI
flags: 0x20
IRQCHIP_ONESHOT_SAFE
parent:
domain: :soc@0:interrupt-controller@0e001000:its@0e050000-5
hwirq: 0x2003
chip: ITS
flags: 0x0
parent:
domain: :soc@0:interrupt-controller@0e001000-1
hwirq: 0x2003
chip: GICv3
flags: 0x15
IRQCHIP_SET_TYPE_MASKED
IRQCHIP_MASK_ON_SUSPEND
IRQCHIP_SKIP_SET_WAKE
msix:
address_hi: 0x00000000
address_lo: 0x0e060040
msg_data: 0x00000002
root@root:/sys/kernel/debug/irq/irqs# cat 89
handler: handle_fasteoi_irq
device: 0000:91:00.0
status: 0x00000000
istate: 0x00004000
ddepth: 0
wdepth: 0
dstate: 0x31600200
IRQD_ACTIVATED
IRQD_IRQ_STARTED
IRQD_SINGLE_TARGET
IRQD_AFFINITY_MANAGED
IRQD_AFFINITY_ON_ACTIVATE
IRQD_HANDLE_ENFORCE_IRQCTX
node: 0
affinity: 2
effectiv: 2
domain: :soc@0:interrupt-controller@0e001000:its@0e050000-3
hwirq: 0x4880003
chip: ITS-MSI
flags: 0x20
IRQCHIP_ONESHOT_SAFE
parent:
domain: :soc@0:interrupt-controller@0e001000:its@0e050000-5
hwirq: 0x2004
chip: ITS
flags: 0x0
parent:
domain: :soc@0:interrupt-controller@0e001000-1
hwirq: 0x2004
chip: GICv3
flags: 0x15
IRQCHIP_SET_TYPE_MASKED
IRQCHIP_MASK_ON_SUSPEND
IRQCHIP_SKIP_SET_WAKE
msix:
address_hi: 0x00000000
address_lo: 0x0e060040
msg_data: 0x00000003

Next message: Neeraj Upadhyay: "[RFC PATCH 07/19] KVM: SEV: Do not intercept SECURE_AVIC_CONTROL MSR"
Previous message: Neeraj Upadhyay: "[RFC PATCH 06/19] KVM: SVM: Initialize apic protected state for SAVIC guests"
In reply to: Thomas Gleixner: "Re: [PATCH] genirq/msi: Add the address and data that show MSI/MSIX"
Next in thread: Thomas Gleixner: "Re: [PATCH] genirq/msi: Add the address and data that show MSI/MSIX"
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