[PATCH v1 01/40] x86/cacheinfo: Validate cpuid leaf 0x2 EDX output

[Ahmed S. Darwish]

cpuid leaf 0x2 emits one-byte descriptors in its four output registers
EAX, EBX, ECX, and EDX.  For these descriptors to be valid, the most
significant bit (MSB) of each register must be clear.

The historical git commit (019361a20f016: "- pre6: Intel: start to add
Pentium IV specific stuff (128-byte cacheline etc)...") introduced leaf
0x2 output parsing.  It only validated the MSBs of EAX, EBX, and ECX,
but left EDX unchecked.

Validate EDX's most-significant bit.

Cc: stable@xxxxxxxxxxxxxxx
Signed-off-by: Ahmed S. Darwish <darwi@xxxxxxxxxxxxx>
---
 arch/x86/kernel/cpu/cacheinfo.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index e6fa03ed9172..a6c6bccfa8b8 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -808,7 +808,7 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c)
 			cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);
 
 			/* If bit 31 is set, this is an unknown format */
-			for (j = 0 ; j < 3 ; j++)
+			for (j = 0 ; j < 4 ; j++)
 				if (regs[j] & (1 << 31))
 					regs[j] = 0;
 
-- 
2.48.1