Re: [PATCH v7 2/2] cxl/pci: Add trace logging for CXL PCIe Port RAS errors

[Alison Schofield]

On Tue, Mar 04, 2025 at 01:10:11PM -0800, Alison Schofield wrote:
> On Tue, Mar 04, 2025 at 12:33:56PM -0800, Koralahalli Channabasappa, Smita wrote:
> snip
> > > > +TRACE_EVENT(cxl_port_aer_uncorrectable_error,
> > > > +	TP_PROTO(struct device *dev, u32 status, u32 fe, u32 *hl),
> > > > +	TP_ARGS(dev, status, fe, hl),
> > > > +	TP_STRUCT__entry(
> > > > +		__string(devname, dev_name(dev))
> > > > +		__string(parent, dev_name(dev->parent))
> > > 
> > > Above devname, parent
> > 
> > Ok I'm planning to keep as device and parent. Let me know if wording "host"
> > is preferred over "parent".
> 
> Take a look at these in the same file that use memdev, 'host'.
> Maybe you want to be similar.
> 
> TRACE_EVENT(cxl_aer_uncorrectable_error,
> TRACE_EVENT(cxl_aer_correctable_error,

BTW - I wasn't being intentionally vague. I don't know what is the
best lingo. Do memdev's have hosts and ports have parents? If
that's the right lingo, then go with it. 


> 
> snip
> > 
>