Re: [PATCH v3 6/9] soc: qcom: geni-se: Add support to load QUP SE Firmware via Linux subsystem

From: kernel test robot
Date: Wed Mar 05 2025 - 13:21:10 EST

Hi Viken,

kernel test robot noticed the following build warnings:

[auto build test WARNING on andi-shyti/i2c/i2c-host]
[also build test WARNING on robh/for-next tty/tty-testing tty/tty-next tty/tty-linus linus/master v6.14-rc5 next-20250305]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url: https://github.com/intel-lab-lkp/linux/commits/Viken-Dadhaniya/dt-bindings-qcom-geni-se-Add-firmware-name-property-for-firmware-loading/20250303-204936
base: https://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux.git i2c/i2c-host
patch link: https://lore.kernel.org/r/20250303124349.3474185-7-quic_vdadhani%40quicinc.com
patch subject: [PATCH v3 6/9] soc: qcom: geni-se: Add support to load QUP SE Firmware via Linux subsystem
config: mips-randconfig-r131-20250305 (https://download.01.org/0day-ci/archive/20250306/202503060145.gERd9R0P-lkp@xxxxxxxxx/config)
compiler: clang version 21.0.0git (https://github.com/llvm/llvm-project 14170b16028c087ca154878f5ed93d3089a965c6)
reproduce: (https://download.01.org/0day-ci/archive/20250306/202503060145.gERd9R0P-lkp@xxxxxxxxx/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@xxxxxxxxx>
| Closes: https://lore.kernel.org/oe-kbuild-all/202503060145.gERd9R0P-lkp@xxxxxxxxx/

sparse warnings: (new ones prefixed by >>)
>> drivers/soc/qcom/qcom-geni-se.c:1215:9: sparse: sparse: cast removes address space '__iomem' of expression
>> drivers/soc/qcom/qcom-geni-se.c:1215:9: sparse: sparse: cast removes address space '__iomem' of expression
>> drivers/soc/qcom/qcom-geni-se.c:1215:9: sparse: sparse: cast removes address space '__iomem' of expression

vim +/__iomem +1215 drivers/soc/qcom/qcom-geni-se.c

1112
1113 /**
1114 * geni_load_se_fw() - Load Serial Engine specific firmware.
1115 * @rsc: Pointer to a structure representing SE-related resources.
1116 * @fw: Pointer to the firmware structure.
1117 *
1118 * Load the protocol firmware into the IRAM of the Serial Engine.
1119 *
1120 * Return: 0 if successful, otherwise return an error value.
1121 */
1122 static int geni_load_se_fw(struct qup_se_rsc *rsc, const struct firmware *fw)
1123 {
1124 const u32 *fw_val_arr, *cfg_val_arr;
1125 const u8 *cfg_idx_arr;
1126 u32 i, reg_value, mask, ramn_cnt;
1127 int ret;
1128 struct elf_se_hdr *hdr;
1129 struct elf32_phdr *phdr;
1130
1131 ret = geni_icc_set_bw(rsc->se);
1132 if (ret) {
1133 dev_err(rsc->se->dev, "%s: Failed to set ICC BW %d\n", __func__, ret);
1134 return ret;
1135 }
1136
1137 ret = geni_icc_enable(rsc->se);
1138 if (ret) {
1139 dev_err(rsc->se->dev, "%s: Failed to enable ICC %d\n", __func__, ret);
1140 return ret;
1141 }
1142
1143 ret = geni_se_resources_on(rsc->se);
1144 if (ret) {
1145 dev_err(rsc->se->dev, "%s: Failed to enable common clocks %d\n", __func__, ret);
1146 goto err;
1147 }
1148
1149 ret = read_elf(rsc, fw, &hdr, &phdr);
1150 if (ret) {
1151 dev_err(rsc->se->dev, "%s: ELF parsing failed ret: %d\n", __func__, ret);
1152 goto err;
1153 }
1154
1155 fw_val_arr = (const u32 *)((u8 *)hdr + hdr->fw_offset);
1156 cfg_idx_arr = (const u8 *)hdr + hdr->cfg_idx_offset;
1157 cfg_val_arr = (const u32 *)((u8 *)hdr + hdr->cfg_val_offset);
1158
1159 geni_config_common_control(rsc);
1160
1161 /* Allows to drive corresponding data according to hardware value. */
1162 writel_relaxed(0x0, rsc->se->base + GENI_OUTPUT_CTRL);
1163
1164 /* Set SCLK and HCLK to program RAM */
1165 setbits32(rsc->se->base + GENI_CGC_CTRL, GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK |
1166 GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK);
1167 writel_relaxed(0x0, rsc->se->base + SE_GENI_CLK_CTRL);
1168 clrbits32(rsc->se->base + GENI_CGC_CTRL, GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK |
1169 GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK);
1170
1171 /* Enable required clocks for DMA CSR, TX and RX. */
1172 reg_value = DMA_GENERAL_CFG_AHB_SEC_SLV_CLK_CGC_ON_BMSK |
1173 DMA_GENERAL_CFG_DMA_AHB_SLV_CLK_CGC_ON_BMSK |
1174 DMA_GENERAL_CFG_DMA_TX_CLK_CGC_ON_BMSK |
1175 DMA_GENERAL_CFG_DMA_RX_CLK_CGC_ON_BMSK;
1176
1177 setbits32(rsc->se->base + DMA_GENERAL_CFG, reg_value);
1178
1179 /* Let hardware control CGC by default. */
1180 writel_relaxed(DEFAULT_CGC_EN, rsc->se->base + GENI_CGC_CTRL);
1181
1182 /* Set version of the configuration register part of firmware. */
1183 writel_relaxed(hdr->cfg_version, rsc->se->base + GENI_INIT_CFG_REVISION);
1184 writel_relaxed(hdr->cfg_version, rsc->se->base + GENI_S_INIT_CFG_REVISION);
1185
1186 /* Configure GENI primitive table. */
1187 for (i = 0; i < hdr->cfg_size_in_items; i++)
1188 writel_relaxed(cfg_val_arr[i],
1189 rsc->se->base + GENI_CFG_REG0 + (cfg_idx_arr[i] * sizeof(u32)));
1190
1191 /* Configure condition for assertion of RX_RFR_WATERMARK condition. */
1192 reg_value = readl_relaxed(rsc->se->base + QUPV3_SE_HW_PARAM_1);
1193 mask = (reg_value >> RX_FIFO_WIDTH_BIT) & RX_FIFO_WIDTH_MASK;
1194 writel_relaxed(mask - 2, rsc->se->base + GENI_RX_RFR_WATERMARK_REG);
1195
1196 /* Let hardware control CGC */
1197 setbits32(rsc->se->base + GENI_OUTPUT_CTRL, DEFAULT_IO_OUTPUT_CTRL_MSK);
1198
1199 ret = geni_configure_xfer_mode(rsc);
1200 if (ret)
1201 goto err_resource;
1202
1203 geni_enable_interrupts(rsc);
1204
1205 geni_flash_fw_revision(rsc, hdr);
1206
1207 ramn_cnt = hdr->fw_size_in_items;
1208 if (hdr->fw_size_in_items % 2 != 0)
1209 ramn_cnt++;
1210
1211 if (ramn_cnt >= MAX_GENI_CFG_RAMn_CNT)
1212 goto err_resource;
1213
1214 /* Program RAM address space. */
> 1215 memcpy((void *)(rsc->se->base + SE_GENI_CFG_RAMN), fw_val_arr, ramn_cnt * sizeof(u32));
1216
1217 /* Put default values on GENI's output pads. */
1218 writel_relaxed(0x1, rsc->se->base + GENI_FORCE_DEFAULT_REG);
1219
1220 /* High to low SCLK and HCLK to finish RAM. */
1221 setbits32(rsc->se->base + GENI_CGC_CTRL, GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK |
1222 GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK);
1223 setbits32(rsc->se->base + SE_GENI_CLK_CTRL, GENI_CLK_CTRL_SER_CLK_SEL_BMSK);
1224 clrbits32(rsc->se->base + GENI_CGC_CTRL, GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK |
1225 GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK);
1226
1227 /* Serial engine DMA interface is enabled. */
1228 setbits32(rsc->se->base + SE_DMA_IF_EN, DMA_IF_EN_DMA_IF_EN_BMSK);
1229
1230 /* Enable or disable FIFO interface of the serial engine. */
1231 if (rsc->mode == GENI_SE_FIFO)
1232 clrbits32(rsc->se->base + SE_FIFO_IF_DISABLE, FIFO_IF_DISABLE);
1233 else
1234 setbits32(rsc->se->base + SE_FIFO_IF_DISABLE, FIFO_IF_DISABLE);
1235
1236 err_resource:
1237 geni_se_resources_off(rsc->se);
1238 err:
1239 geni_icc_disable(rsc->se);
1240 return ret;
1241 }
1242

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