Re: [PATCH v4 12/14] clk: sunxi-ng: a523: add bus clock gates

[Jernej Škrabec]

Dne petek, 7. marec 2025 ob 01:26:26 Srednjeevropski standardni čas je Andre Przywara napisal(a):
> Add the various bus clock gates that control access to the devices'
> register interface.
> These clocks are each just one bit, typically the lower bits in some "BGR"
> (Bus Gate / Reset) registers, for each device group: one for all UARTs,
> one for all SPI interfaces, and so on.
> 
> Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx>

Reviewed-by: Jernej Skrabec <jernej.skrabec@xxxxxxxxx>

Best regards,
Jernej