RE: [PATCH v2 1/3] dt-binding: aspeed: Add LPC PCC controller

[Kevin Chen]

> On 10/03/2025 10:49, Kevin Chen wrote:
> >>>>> +            compatible = "aspeed,ast2600-lpc-pcc";
> >>>>> +            reg = <0x0 0x140>;
> >>>>> +            interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
> >>>>> +            pcc-ports = <0x80>;
> >>>>
> >>>> So what 0x80 stands for?
> >>> Host as x86 architecture would access the 0x80 port, which is mapped to
> the
> >> BMC PCC HW module.
> >>> As a result, x86 can keep the port-mmaped I/O usage and access the BMC
> >> device, which is needed to know which port using in the PCC module in
> BMC.
> >>
> >> And on different boards this is not 0x80?
> > The port-mmaped I/O defined in the intel legacy document as the example
> usage.
> > For example, the common usage agreement of port-mmaped I/O are the
> following. But this setting can be modified due to the host usage. We provide
> the flexibility to modify the I/O port settings.
> > KCS : 0xCA2(CMD)/CA3(Data)
> > BT : 0xE4/E5/E6
> > SNOOP/PCC : 0x80/81/82/83
> > Mailbox : 0xCC0
> > SuperIO : 0x2E/2F or 0x4E/0x4F
> > System UART : 0x3F8/2F8/3E8/2E8
> So which boards have it modified?
This setting should be as same as the snoop-ports. You can check the dts in arch/arm/boot/dts/aspeed folder.
aspeed-bmc-amd-daytonax.dts
212:    snoop-ports = <0x80>, <0x81>;

aspeed-bmc-facebook-tiogapass.dts
77:     snoop-ports = <0x80>;


> 
> Best regards,
> Krzysztof