Re: [PATCH v7 3/4] PCI: dwc: Improve handling of PCIe lane configuration

[Krishna Chaitanya Chundru]

On 3/6/2025 9:14 AM, Manivannan Sadhasivam wrote:
> On Tue, Feb 25, 2025 at 05:15:06PM +0530, Krishna Chaitanya Chundru wrote:
> > Currently even if the number of lanes hardware supports is equal to
> > the number lanes provided in the devicetree, the driver is trying to
> > configure again the maximum number of lanes which is not needed.
> >
> > Update number of lanes only when it is not equal to hardware capability.
>
> 'Update max link width only...'
>
> > And also if the num-lanes property is not present in the devicetree
> > update the num_lanes with the maximum hardware supports.
>
> '...update 'pci->num_lanes' with the hardware supported maximum link width using
> the newly introduced dw_pcie_link_get_max_link_width() API.'
>
> > Introduce dw_pcie_link_get_max_link_width() to get the maximum lane
> > width the hardware supports.
> >
> > Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx>
> > ---
> >   drivers/pci/controller/dwc/pcie-designware-host.c |  3 +++
> >   drivers/pci/controller/dwc/pcie-designware.c      | 11 ++++++++++-
> >   drivers/pci/controller/dwc/pcie-designware.h      |  1 +
> >   3 files changed, 14 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> > index ffaded8f2df7..dd56cc02f4ef 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> > @@ -504,6 +504,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
> >   
> >   	dw_pcie_iatu_detect(pci);
> >   
> > +	if (pci->num_lanes < 1)
> > +		pci->num_lanes = dw_pcie_link_get_max_link_width(pci);
> > +
> >   	/*
> >   	 * Allocate the resource for MSG TLP before programming the iATU
> >   	 * outbound window in dw_pcie_setup_rc(). Since the allocation depends
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > index 145e7f579072..9fc5916867b6 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > @@ -737,12 +737,21 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci)
> >   
> >   }
> >   
> > +int dw_pcie_link_get_max_link_width(struct dw_pcie *pci)
> > +{
> > +	u8 cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > +	u32 lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
> > +
> > +	return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap);
> > +}
> > +
> >   static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> >   {
> > +	int max_lanes = dw_pcie_link_get_max_link_width(pci);
> >   	u32 lnkcap, lwsc, plc;
> >   	u8 cap;
> >   
> > -	if (!num_lanes)
> > +	if (max_lanes == num_lanes)
>
> This gives the assumption that the link width in PCIE_PORT_LINK_CONTROL and
> PCIE_LINK_WIDTH_SPEED_CONTROL registers are same as MLW. Is it really true as
> per the DWC spec?
You are correct both the values are not matching and as we are not sure
side effect of not updating it I will revert this logic.

- Krishna Chaitanya.
> - Mani