[PATCH v2 1/3] dt-bindings: mtd: microchip-nand: convert txt to yaml
From: Balamanikandan Gunasundar
Date: Tue Mar 11 2025 - 08:34:28 EST
Convert text to yaml for microchip nand controller
Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@xxxxxxxxxxxxx>
---
Changes in v2:
- Change the filename to match the compatible string
- Drop items and oneOf in the compatible property as it is just an enum
- Remove the if in the #address-cells and #size-cells
- Remove the unwanted comments that refers to .txt files
- Fix reg property description
- Define the properties in a list and add constraints
- Fix DT coding style and droped unused labels
.../devicetree/bindings/mtd/atmel-nand.txt | 50 -----
.../mtd/microchip,nand-controller.yaml | 175 ++++++++++++++++++
2 files changed, 175 insertions(+), 50 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mtd/microchip,nand-controller.yaml
diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
index e36c35b17873..dbbc17a866f2 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
@@ -1,53 +1,3 @@
-Atmel NAND flash controller bindings
-
-The NAND flash controller node should be defined under the EBI bus (see
-Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
-One or several NAND devices can be defined under this NAND controller.
-The NAND controller might be connected to an ECC engine.
-
-* NAND controller bindings:
-
-Required properties:
-- compatible: should be one of the following
- "atmel,at91rm9200-nand-controller"
- "atmel,at91sam9260-nand-controller"
- "atmel,at91sam9261-nand-controller"
- "atmel,at91sam9g45-nand-controller"
- "atmel,sama5d3-nand-controller"
- "microchip,sam9x60-nand-controller"
-- ranges: empty ranges property to forward EBI ranges definitions.
-- #address-cells: should be set to 2.
-- #size-cells: should be set to 1.
-- atmel,nfc-io: phandle to the NFC IO block. Only required for sama5d3
- controllers.
-- atmel,nfc-sram: phandle to the NFC SRAM block. Only required for sama5d3
- controllers.
-
-Optional properties:
-- ecc-engine: phandle to the PMECC block. Only meaningful if the SoC embeds
- a PMECC engine.
-
-* NAND device/chip bindings:
-
-Required properties:
-- reg: describes the CS lines assigned to the NAND device. If the NAND device
- exposes multiple CS lines (multi-dies chips), your reg property will
- contain X tuples of 3 entries.
- 1st entry: the CS line this NAND chip is connected to
- 2nd entry: the base offset of the memory region assigned to this
- device (always 0)
- 3rd entry: the memory region size (always 0x800000)
-
-Optional properties:
-- rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND.
-- cs-gpios: the GPIO(s) used to control the CS line.
-- det-gpios: the GPIO used to detect if a Smartmedia Card is present.
-- atmel,rb: an integer identifying the native Ready/Busy pin. Only meaningful
- on sama5 SoCs.
-
-All generic properties are described in the generic yaml files under
-Documentation/devicetree/bindings/mtd/.
-
* ECC engine (PMECC) bindings:
Required properties:
diff --git a/Documentation/devicetree/bindings/mtd/microchip,nand-controller.yaml b/Documentation/devicetree/bindings/mtd/microchip,nand-controller.yaml
new file mode 100644
index 000000000000..bf644ab0cf27
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/microchip,nand-controller.yaml
@@ -0,0 +1,175 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/microchip,nand-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip NAND flash controller
+
+maintainers:
+ - Balamanikandan Gunasundar <balamanikandan.gunasundar@xxxxxxxxxxxxx>
+
+description: |
+ The NAND flash controller node should be defined under the EBI bus (see
+ Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
+ One or several NAND devices can be defined under this NAND controller.
+ The NAND controller might be connected to an ECC engine.
+
+properties:
+ compatible:
+ enum:
+ - atmel,at91rm9200-nand-controller
+ - atmel,at91sam9260-nand-controller
+ - atmel,at91sam9261-nand-controller
+ - atmel,at91sam9g45-nand-controller
+ - atmel,sama5d3-nand-controller
+ - microchip,sam9x60-nand-controller
+
+ ranges:
+ description: empty ranges property to forward EBI ranges definitions.
+
+ ecc-engine:
+ description:
+ phandle to the PMECC block. Only meaningful if the SoC embeds a PMECC
+ engine.
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 1
+
+ atmel,nfc-io:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the NFC IO block. Only applicable for atmel,sama5d3-nand-controller
+
+ atmel,nfc-sram:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the NFC SRAM block. Only applicable for atmel,sama5d3-nand-controller
+
+required:
+ - compatible
+ - ranges
+ - "#address-cells"
+ - "#size-cells"
+
+patternProperties:
+ "^nand@[a-f0-9]$":
+ type: object
+ $ref: raw-nand-chip.yaml#
+ description:
+ NAND chip bindings.
+
+ additionalProperties: false
+
+ properties:
+ reg:
+ items:
+ - items:
+ - description: describes the CS lines assigned to the NAND device.
+ - description: the base offset of the memory region assigned to this device (always 0)
+ - description: the memory region size (always 0x800000)
+ rb-gpios:
+ description:
+ the GPIO(s) used to check the Ready/Busy status of the NAND.
+
+ cs-gpios:
+ description:
+ the GPIO(s) used to control the CS line.
+
+ det-gpios:
+ description:
+ the GPIO used to detect if a Smartmedia Card is present.
+
+ atmel,rb:
+ description: |
+ an integer identifying the native Ready/Busy pin.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ nand-ecc-step-size:
+ const: 512
+
+ nand-ecc-strength:
+ enum: [2, 4, 8]
+
+ nand-ecc-mode:
+ enum: [soft, hw]
+
+ nand-bus-width:
+ const: 8
+
+ nand-on-flash-bbt: true
+
+ partitions:
+ $ref: /schemas/mtd/partitions/partitions.yaml
+
+ label:
+ description: Name or Label of the device
+
+ allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: atmel,sama5d3-nand-controller
+ then:
+ properties:
+ "atmel,rb":
+ description: an integer identifying the native Ready/Busy pin.
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ nfc_io: nfc-io@70000000 {
+ compatible = "atmel,sama5d3-nfc-io", "syscon";
+ reg = <0x70000000 0x8000000>;
+ };
+
+ nfc_sram: sram@200000 {
+ compatible = "mmio-sram";
+ no-memory-wc;
+ reg = <0x200000 0x2400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x200000 0x2400>;
+ };
+
+ pmecc: ecc-engine@ffffc070 {
+ compatible = "atmel,at91sam9g45-pmecc";
+ reg = <0xffffc070 0x490>,
+ <0xffffc500 0x100>;
+ };
+
+ ebi@10000000 {
+ compatible = "atmel,sama5d3-ebi";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ atmel,smc = <&hsmc>;
+ reg = <0x10000000 0x10000000
+ 0x40000000 0x30000000>;
+ ranges = <0x0 0x0 0x10000000 0x10000000
+ 0x1 0x0 0x40000000 0x10000000
+ 0x2 0x0 0x50000000 0x10000000
+ 0x3 0x0 0x60000000 0x10000000>;
+ clocks = <&mck>;
+
+ nand_controller: nand-controller {
+ compatible = "atmel,sama5d3-nand-controller";
+ atmel,nfc-sram = <&nfc_sram>;
+ atmel,nfc-io = <&nfc_io>;
+ ecc-engine = <&pmecc>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ atmel,rb = <0>;
+ /*
+ * Put generic NAND/MTD properties and
+ * subnodes here.
+ */
+ };
+ };
+ };
--
2.34.1