Re: [PATCH v8 2/2] cxl/pci: Add trace logging for CXL PCIe Port RAS errors

[Li Ming]

On 3/11/2025 6:38 AM, Smita Koralahalli wrote:
> The CXL drivers use kernel trace functions for logging endpoint and
> Restricted CXL host (RCH) Downstream Port RAS errors. Similar functionality
> is required for CXL Root Ports, CXL Downstream Switch Ports, and CXL
> Upstream Switch Ports.
>
> Introduce trace logging functions for both RAS correctable and
> uncorrectable errors specific to CXL PCIe Ports. Use them to trace
> FW-First Protocol errors.
>
> Co-developed-by: Terry Bowman <terry.bowman@xxxxxxx>
> Signed-off-by: Terry Bowman <terry.bowman@xxxxxxx>
> Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@xxxxxxx>
> Reviewed-by: Ira Weiny <ira.weiny@xxxxxxxxx>

Reviewed-by: Li Ming <ming.li@xxxxxxxxxxxx>