[PATCH 1/2] dt-bindings: mailbox: cix: add device tree binding documentation.

From: Guomin Chen
Date: Thu Mar 13 2025 - 09:22:33 EST


From: Guomin Chen <Guomin.Chen@xxxxxxxxxxx>

This patch adds device tree binding for mailbox from Cixtech.

Reviewed-by: Peter Chen <peter.chen@xxxxxxxxxxx>
Signed-off-by: Lihua Liu <Lihua.Liu@xxxxxxxxxxx>
Signed-off-by: Guomin Chen <Guomin.Chen@xxxxxxxxxxx>
---
.../bindings/mailbox/cix-mailbox.yaml | 74 +++++++++++++++++++
1 file changed, 74 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mailbox/cix-mailbox.yaml

diff --git a/Documentation/devicetree/bindings/mailbox/cix-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/cix-mailbox.yaml
new file mode 100644
index 000000000000..85cb54ae2e79
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/cix-mailbox.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/cix-mailbox.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cix mailbox controller
+
+maintainers:
+ - Lihua Liu <Lihua.Liu@xxxxxxxxxxx>
+
+description:
+ CIX mailbox controller is used to exchange message within
+ multiple processors, such as AP, AUDIO DSP, SensorHub MCU,
+ etc. It supports 10 mailbox channels with different operating
+ mode and every channel is unidirectional.
+
+properties:
+ compatible:
+ const: cix,sky1-mbox
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ "#mbox-cells":
+ description: |
+ <&phandle channel>
+ phandle : Label name of controller
+ channel : Channel number
+
+ This controller supports three types of unidirectional channels, they are
+ 1 register based channel, 1 fifo based channel and 8 fast channels.
+ A total of 10 channels for each controller. Following types are
+ supported:
+ channel 0_7 - Fast channel with 32bit transmit register and IRQ support.
+ channel 8 - Reg based channel with 32*32bit transsmit register and
+ Doorbell+transmit acknowledgment IRQ support
+ channel 9 - Fifo based channel with 32*32bit depth fifo and IRQ support.
+ const: 1
+
+ cix,mbox-dir:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Direction of the mailbox (0:TX or 1:RX)
+ enum: [0, 1]
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#mbox-cells"
+ - cix,mbox-dir
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ mbox0: mailbox@30000000 {
+ compatible = "cix,sky1-mbox";
+ reg = <0 0x30000000 0 0x10000>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <1>;
+ cix,mbox-dir = <0>;
+ status = "okay";
+ };
+ };
--
2.34.1