Re: [PATCH V5] usb:xhci: Add debugfs support for xHCI port bandwidth

[Mathias Nyman]

On 13.3.2025 15.21, raoxu wrote:
> From: Xu Rao <raoxu@xxxxxxxxxxxxx>
>
> In many projects, you need to obtain the available bandwidth of the
> xhci roothub port. Refer to xhci rev1_2 and use the TRB_GET_BW
> command to obtain it.
>
> hardware tested:
> 03:00.3 USB controller: Advanced Micro Devices, Inc. [AMD] Raven USB 3.1
> (prog-if 30 [XHCI])
> Subsystem: Huawei Technologies Co., Ltd. Raven USB 3.1
> Flags: bus master, fast devsel, latency 0, IRQ 30
> Memory at c0300000 (64-bit, non-prefetchable) [size=1M]
> Capabilities: [48] Vendor Specific Information: Len=08 <?>
> Capabilities: [50] Power Management version 3
> Capabilities: [64] Express Endpoint, MSI 00
> Capabilities: [a0] MSI: Enable- Count=1/8 Maskable- 64bit+
> Capabilities: [c0] MSI-X: Enable+ Count=8 Masked-
> Kernel driver in use: xhci_hcd

...

> @@ -2463,7 +2497,16 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
>   	 * will be allocated with dma_alloc_coherent()
>   	 */
>
> -	if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
> +	/* refer to xhci rev1_2 protocol 5.3.3 max ports is 255.
> +	 * refer to xhci rev1_2 protocol 6.2.6 port bandwidth buffer need to be
> +	 * 8-byte aligned.
> +	 */

The context size needs to be rounded up to nearest 8-byte boundary.
We allocate 256 bytes so we are covered.

Specification unfortunately fails to mention about the 16-byte context alignment
requirement here in section 6.2.6 'Port Bandwith Context'.

This info is hidden in section 6.4.3.14 'Get Port Bandwidth Command TRB' in
'Port Bandwidth Context Pointer Hi and Lo' field 63:4

"The memory structure referenced by this physical memory pointer shall be aligned
 on a 16-byte address boundary."

> +	xhci->port_bw_pool =
> +		dma_pool_create("xHCI 256 port bw ctx arrays",
> +			dev, GET_PORT_BW_ARRAY_SIZE, 8, 0);

Thanks
Mathias