Re: [PATCH v7 06/10] iio: adc: Support ROHM BD79124 ADC

[Andy Shevchenko]

On Fri, Mar 14, 2025 at 11:22:37AM +0200, Matti Vaittinen wrote:
> On 13/03/2025 15:19, Andy Shevchenko wrote:
> > On Thu, Mar 13, 2025 at 09:19:03AM +0200, Matti Vaittinen wrote:

...

> > > +	ret = regmap_read(data->map, BD79124_REG_EVENT_FLAG_HI, &i_hi);
> > > +	if (ret)
> > > +		return IRQ_NONE;
> > > +
> > > +	ret = regmap_read(data->map, BD79124_REG_EVENT_FLAG_LO, &i_lo);
> > > +	if (ret)
> > > +		return IRQ_NONE;
> > 
> > Only I don't get why you can't use bulk read here.
> > The registers seem to be sequential.
> 
> After taking another look - there seems to be undocumented register (0x1b)
> between the BD79124_REG_EVENT_FLAG_HI (0x1a) and the
> BD79124_REG_EVENT_FLAG_LO (0x1c).
> 
> I won't touch it unless there is a real verified performance problem.

...

> > In the similar way bulk write.
> 
> definitely not due to the 0x1b.

Okay, it seems I misinterpreted the values you have in regmap configuration,
I was under the impression that regmap is 16-bit data, but it is about address.

So, we need to know why the heck HW has sparse registers for what is supposed
to be sequential. This needs a good comment.

-- 
With Best Regards,
Andy Shevchenko