On Thu, 13 Mar 2025 09:19:03 +0200
Matti Vaittinen <mazziesaccount@xxxxxxxxx> wrote:
The ROHM BD79124 is a 12-bit, 8-channel, SAR ADC. The ADC supportsGiven you are going to be doing a v8 and I'm bored on a train, so utterly
an automatic measurement mode, with an alarm interrupt for out-of-window
measurements. The window is configurable for each channel.
The I2C protocol for manual start of the measurement and data reading is
somewhat peculiar. It requires the master to do clock stretching after
sending the I2C slave-address until the slave has captured the data.
Needless to say this is not well suopported by the I2C controllers.
Thus the driver does not support the BD79124's manual measurement mode
trivial comments that you get as a frequent contributor as things to
consider for future patches. (I'm sure it's just what you always wanted
:)
In theory should be imperative though I don't care as much as some.
Hence, do not support the....
but implements the measurements using automatic measurement mode relyingTrivial editorial comment: that 'does' is not providing anything use
on the BD79124's ability of storing latest measurements into register.
The driver does also support configuring the threshold events for
detecting the out-of-window events.
in modern English (might have done in the past, no idea!)
"Also support configure the threshold..."
The BD79124 keeps asserting IRQ for as long as the measured voltage is
out of the configured window. Thus the driver masks the received event
for a fixed duration (1 second) when an event is handled. This prevents
the user-space from choking on the events
The ADC input pins can be also configured as general purpose outputs.
Those pins which don't have corresponding ADC channel node in the
device-tree will be controllable as GPO.
Signed-off-by: Matti Vaittinen <mazziesaccount@xxxxxxxxx>
A few trivial things inline.
Jonathan
+/*Convert?
+ * The high and low limits as well as the recent result values are stored in
+ * the same way in 2 consequent registers. The first register contains 4 bits
+ * of the value. These bits are stored in the high bits [7:4] of register, but
+ * they represent the low bits [3:0] of the value.
+ * The value bits [11:4] are stored in the next regoster.
+ *
+ * Conver the integer to register format and write it using rmw cycle.