Fwd: Failure in triggering jd9365da MIPI DSI Display drm_panel functions prepare/enable()

From: nelakurthi koteswararao
Date: Tue Mar 18 2025 - 07:32:11 EST

Hi,
Requesting to please go through below mail that deals with MIPI DSI display panel bringup activity.

Jd9365da  is  a MIPI dsi panel is connected to nxp based imx8mm core board directly without any bridge and it’s connected through MIPI DSIM (SAMSUNG)  (linux-6.6/drivers/gpu/drm/Bridge/Samsung-dsim.c) software interface.

Prepared Scarthgap yocto BSP images for imx8mm core based NXP  board  running with linux-6.6 kernel version and booted the board.

The below log in boot sequence  confirm panel is attached with dsim host controller.  

{{

[    2.568380] samsung-dsim 32e10000.dsi: [drm:samsung_dsim_host_attach] Attached display-8hd-a device // printed from samsung_dsim_host_attach()  in drivers/gpu/drm/bridge/samsung-dsim.c

}}

But The issue I am facing currently is DRM pipeline is failing to trigger struct drm_bridge_funcs attach() definition i.e Samsung_dsim_attach() that in turn invokes drm_bridge_attach() and it helps in triggering Jd9365da drm_panel specific prepare/enable functions subsequently.

I attached a debug log added  to Samsung-dsim.c file along with a jd9365da panel file (with debug logs) and boot log for reference. I attached jd9365da dts file too for reference

I request to please go through attached files and boot logs and please provide input for further debugging. 

I attached an arch/arm64/boot/dts/freescale/imx8mm.dtsi file (that contains mipi-dsi entries for Samsung-dsim.c) .


Kind Regards

Kote

[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[ 0.000000] Linux version 6.6.52eng-6.6-g978fbc7d6c7c-dirty (oe-user@oe-host) (aarch64-poky-linux-gcc (GCC) 13.3.0, GNU ld (GNU Binutils) 2.42.0.20240723) #1 SMP PREEMPT Tue Mar 4 14:49:57 UTC 2025
[ 0.000000] KASLR disabled due to lack of seed
[ 0.000000] Machine model: Engicam i.Core MX8MM Starterkit 2.1
[ 0.000000] efi: UEFI not found.
[ 0.000000] Reserved memory: created CMA memory pool at 0x0000000058000000, size 640 MiB
[ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
[ 0.000000] OF: reserved mem: 0x0000000058000000..0x000000007fffffff (655360 KiB) map reusable linux,cma
[ 0.000000] OF: reserved mem: 0x00000000b8000000..0x00000000b83fffff (4096 KiB) nomap non-reusable rpmsg@b8000000
[ 0.000000] NUMA: No NUMA configuration found
[ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000007fffffff]
[ 0.000000] NUMA: NODE_DATA [mem 0x57dc76c0-0x57dc9fff]
[ 0.000000] Zone ranges:
[ 0.000000] DMA [mem 0x0000000040000000-0x000000007fffffff]
[ 0.000000] DMA32 empty
[ 0.000000] Normal empty
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000040000000-0x000000007fffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000007fffffff]
[ 0.000000] psci: probing for conduit method from DT.
[ 0.000000] psci: PSCIv1.1 detected in firmware.
[ 0.000000] psci: Using standard PSCI v0.2 function IDs
[ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
[ 0.000000] psci: SMC Calling Convention v1.4
[ 0.000000] percpu: Embedded 22 pages/cpu s50536 r8192 d31384 u90112
[ 0.000000] Detected VIPT I-cache on CPU0
[ 0.000000] CPU features: detected: GIC system register CPU interface
[ 0.000000] CPU features: detected: ARM erratum 845719
[ 0.000000] alternatives: applying boot alternatives
[ 0.000000] Kernel command line: console=ttymxc1,115200 root=/dev/mmcblk0p2 rootwait rw
[ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
[ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
[ 0.000000] Fallback order for Node 0: 0
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 258048
[ 0.000000] Policy zone: DMA
[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
[ 0.000000] software IO TLB: area num 4.
[ 0.000000] software IO TLB: mapped [mem 0x0000000052b80000-0x0000000056b80000] (64MB)
[ 0.000000] Memory: 271256K/1048576K available (20928K kernel code, 1624K rwdata, 7704K rodata, 3968K init, 635K bss, 121960K reserved, 655360K cma-reserved)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
[ 0.000000] rcu: RCU event tracing is enabled.
[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=4.
[ 0.000000] Trampoline variant of Tasks RCU enabled.
[ 0.000000] Tracing variant of Tasks RCU enabled.
[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
[ 0.000000] GICv3: 128 SPIs implemented
[ 0.000000] GICv3: 0 Extended SPIs implemented
[ 0.000000] Root IRQ handler: gic_handle_irq
[ 0.000000] GICv3: GICv3 features: 16 PPIs
[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000038880000
[ 0.000000] ITS: No ITS available, not enabling LPIs
[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
[ 0.000000] arch_timer: cp15 timer(s) running at 8.00MHz (phys).
[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 440795202120 ns
[ 0.000000] sched_clock: 56 bits at 8MHz, resolution 125ns, wraps every 2199023255500ns
[ 0.000409] Console: colour dummy device 80x25
[ 0.000468] Calibrating delay loop (skipped), value calculated using timer frequency.. 16.00 BogoMIPS (lpj=32000)
[ 0.000479] pid_max: default: 32768 minimum: 301
[ 0.000543] LSM: initializing lsm=capability,integrity
[ 0.000632] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
[ 0.000642] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
[ 0.002126] RCU Tasks: Setting shift to 2 and lim to 1 rcu_task_cb_adjust=1.
[ 0.002205] RCU Tasks Trace: Setting shift to 2 and lim to 1 rcu_task_cb_adjust=1.
[ 0.002360] rcu: Hierarchical SRCU implementation.
[ 0.002364] rcu: Max phase no-delay instances is 1000.
[ 0.003397] EFI services will not be available.
[ 0.003597] smp: Bringing up secondary CPUs ...
[ 0.004107] Detected VIPT I-cache on CPU1
[ 0.004173] GICv3: CPU1: found redistributor 1 region 0:0x00000000388a0000
[ 0.004216] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
[ 0.004726] Detected VIPT I-cache on CPU2
[ 0.004771] GICv3: CPU2: found redistributor 2 region 0:0x00000000388c0000
[ 0.004793] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
[ 0.005247] Detected VIPT I-cache on CPU3
[ 0.005290] GICv3: CPU3: found redistributor 3 region 0:0x00000000388e0000
[ 0.005312] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
[ 0.005380] smp: Brought up 1 node, 4 CPUs
[ 0.005386] SMP: Total of 4 processors activated.
[ 0.005390] CPU features: detected: 32-bit EL0 Support
[ 0.005393] CPU features: detected: 32-bit EL1 Support
[ 0.005397] CPU features: detected: CRC32 instructions
[ 0.005461] CPU: All CPU(s) started at EL2
[ 0.005483] alternatives: applying system-wide alternatives
[ 0.007059] devtmpfs: initialized
[ 0.013544] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[ 0.013566] futex hash table entries: 1024 (order: 4, 65536 bytes, linear)
[ 0.031997] pinctrl core: initialized pinctrl subsystem
[ 0.033886] DMI not present or invalid.
[ 0.034488] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[ 0.035309] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations
[ 0.035378] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
[ 0.035451] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
[ 0.035497] audit: initializing netlink subsys (disabled)
[ 0.035640] audit: type=2000 audit(0.032:1): state=initialized audit_enabled=0 res=1
[ 0.036176] thermal_sys: Registered thermal governor 'step_wise'
[ 0.036181] thermal_sys: Registered thermal governor 'power_allocator'
[ 0.036214] cpuidle: using governor menu
[ 0.036399] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[ 0.036480] ASID allocator initialised with 65536 entries
[ 0.037395] Serial: AMBA PL011 UART driver
[ 0.037460] imx mu driver is registered.
[ 0.037483] imx rpmsg driver is registered.
[ 0.042878] platform soc@0: Fixed dependency cycle(s) with /soc@0/bus@30000000/efuse@30350000/unique-id@4
[ 0.045681] imx8mm-pinctrl 30330000.pinctrl: initialized IMX pinctrl driver
[ 0.046142] platform 30350000.efuse: Fixed dependency cycle(s) with /soc@0/bus@30000000/clock-controller@30380000
[ 0.047279] platform 30350000.efuse: Fixed dependency cycle(s) with /soc@0/bus@30000000/clock-controller@30380000
[ 0.053044] platform 32e00000.lcdif: Fixed dependency cycle(s) with /soc@0/bus@32c00000/mipi_dsi@32e10000
[ 0.053270] platform 32e00000.lcdif: Fixed dependency cycle(s) with /soc@0/bus@32c00000/mipi_dsi@32e10000
[ 0.053339] platform 32e10000.mipi_dsi: Fixed dependency cycle(s) with /soc@0/bus@32c00000/mipi_dsi@32e10000/panel@0
[ 0.053386] platform 32e10000.mipi_dsi: Fixed dependency cycle(s) with /soc@0/bus@32c00000/lcdif@32e00000
[ 0.053745] platform 32e20000.csi1_bridge: Fixed dependency cycle(s) with /soc@0/bus@32c00000/mipi_csi@32e30000
[ 0.053976] platform 32e20000.csi1_bridge: Fixed dependency cycle(s) with /soc@0/bus@32c00000/mipi_csi@32e30000
[ 0.054085] platform 32e30000.mipi_csi: Fixed dependency cycle(s) with /soc@0/bus@32c00000/csi1_bridge@32e20000
[ 0.054155] platform 32e30000.mipi_csi: Fixed dependency cycle(s) with /soc@0/bus@30800000/i2c@30a30000/ov5640_mipi@3c
[ 0.059996] Modules: 24000 pages in range for non-PLT usage
[ 0.060005] Modules: 515520 pages in range for PLT usage
[ 0.060799] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
[ 0.060806] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
[ 0.060810] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
[ 0.060815] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
[ 0.060819] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
[ 0.060823] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
[ 0.060827] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
[ 0.060830] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
[ 0.062659] ACPI: Interpreter disabled.
[ 0.063604] iommu: Default domain type: Translated
[ 0.063615] iommu: DMA domain TLB invalidation policy: strict mode
[ 0.063926] SCSI subsystem initialized
[ 0.064289] usbcore: registered new interface driver usbfs
[ 0.064315] usbcore: registered new interface driver hub
[ 0.064342] usbcore: registered new device driver usb
[ 0.065373] mc: Linux media interface: v0.10
[ 0.065414] videodev: Linux video capture interface: v2.00
[ 0.065470] pps_core: LinuxPPS API ver. 1 registered
[ 0.065474] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@xxxxxxxx>
[ 0.065485] PTP clock support registered
[ 0.065676] EDAC MC: Ver: 3.0.0
[ 0.066102] scmi_core: SCMI protocol bus registered
[ 0.066398] FPGA manager framework
[ 0.066477] Advanced Linux Sound Architecture Driver Initialized.
[ 0.067180] Bluetooth: Core ver 2.22
[ 0.067209] NET: Registered PF_BLUETOOTH protocol family
[ 0.067213] Bluetooth: HCI device and connection manager initialized
[ 0.067220] Bluetooth: HCI socket layer initialized
[ 0.067225] Bluetooth: L2CAP socket layer initialized
[ 0.067236] Bluetooth: SCO socket layer initialized
[ 0.067576] vgaarb: loaded
[ 0.068038] clocksource: Switched to clocksource arch_sys_counter
[ 0.068309] VFS: Disk quotas dquot_6.6.0
[ 0.068337] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[ 0.068504] pnp: PnP ACPI: disabled
[ 0.075068] NET: Registered PF_INET protocol family
[ 0.075200] IP idents hash table entries: 16384 (order: 5, 131072 bytes, linear)
[ 0.076119] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear)
[ 0.076139] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
[ 0.076150] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear)
[ 0.076249] TCP bind hash table entries: 8192 (order: 6, 262144 bytes, linear)
[ 0.076469] TCP: Hash tables configured (established 8192 bind 8192)
[ 0.076549] UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
[ 0.076576] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
[ 0.076687] NET: Registered PF_UNIX/PF_LOCAL protocol family
[ 0.077022] RPC: Registered named UNIX socket transport module.
[ 0.077026] RPC: Registered udp transport module.
[ 0.077029] RPC: Registered tcp transport module.
[ 0.077031] RPC: Registered tcp-with-tls transport module.
[ 0.077034] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 0.078063] PCI: CLS 0 bytes, default 64
[ 0.078391] kvm [1]: IPA Size Limit: 40 bits
[ 0.080333] kvm [1]: GICv3: no GICV resource entry
[ 0.080338] kvm [1]: disabling GICv2 emulation
[ 0.080357] kvm [1]: GIC system register CPU interface enabled
[ 0.080381] kvm [1]: vgic interrupt IRQ9
[ 0.080403] kvm [1]: Hyp mode initialized successfully
[ 0.081551] Initialise system trusted keyrings
[ 0.081725] workingset: timestamp_bits=42 max_order=18 bucket_order=0
[ 0.081998] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[ 0.082210] NFS: Registering the id_resolver key type
[ 0.082242] Key type id_resolver registered
[ 0.082245] Key type id_legacy registered
[ 0.082262] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[ 0.082267] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
[ 0.082283] jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
[ 0.082472] 9p: Installing v9fs 9p2000 file system support
[ 0.116053] Key type asymmetric registered
[ 0.116059] Asymmetric key parser 'x509' registered
[ 0.116098] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
[ 0.116104] io scheduler mq-deadline registered
[ 0.116108] io scheduler kyber registered
[ 0.116135] io scheduler bfq registered
[ 0.122430] EINJ: ACPI disabled.
[ 0.131178] mxs-dma 33000000.dma-controller: initialized
[ 0.132361] SoC: i.MX8MM revision 1.0
[ 0.132789] Bus freq driver module loaded
[ 0.144719] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[ 0.147520] 30860000.serial: ttymxc0 at MMIO 0x30860000 (irq = 15, base_baud = 5000000) is a IMX
[ 0.148337] 30880000.serial: ttymxc2 at MMIO 0x30880000 (irq = 16, base_baud = 5000000) is a IMX
[ 0.148954] 30890000.serial: ttymxc1 at MMIO 0x30890000 (irq = 17, base_baud = 1500000) is a IMX
[ 0.148980] printk: console [ttymxc1] enabled
[ 1.372982] samsung_dsim_probe entry -------------->
[ 1.378084] samsung-dsim 32e10000.mipi_dsi: supply vddcore not found, using dummy regulator
[ 1.386557] samsung-dsim 32e10000.mipi_dsi: supply vddio not found, using dummy regulator
[ 1.395067] plat_data->hw_type is imx8mm core =========>
[ 1.400490] generic_dsim_register_host entry ==========>
[ 1.406020] samsung-dsim 32e10000.mipi_dsi: Fixed dependency cycle(s) with /soc@0/bus@32c00000/mipi_dsi@32e10000/panel@0
[ 1.417026] mipi-dsi 32e10000.mipi_dsi.0: Fixed dependency cycle(s) with /soc@0/bus@32c00000/mipi_dsi@32e10000
[ 1.427311] samsung_dsim_probe exit =========>
[ 1.434828] lcdif_crtc_probe: lcdif crtc probe begin
[ 1.445849] loop: module loaded
[ 1.450510] megasas: 07.725.01.00-rc1
[ 1.460754] tun: Universal TUN/TAP device driver, 1.6
[ 1.466662] thunder_xcv, ver 1.0
[ 1.469939] thunder_bgx, ver 1.0
[ 1.473196] nicpf, ver 1.0
[ 1.477940] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
[ 1.485173] hns3: Copyright (c) 2017 Huawei Corporation.
[ 1.490529] hclge is initializing
[ 1.493885] e1000: Intel(R) PRO/1000 Network Driver
[ 1.498776] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 1.504552] e1000e: Intel(R) PRO/1000 Network Driver
[ 1.509522] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
[ 1.515471] igb: Intel(R) Gigabit Ethernet Network Driver
[ 1.520877] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 1.526477] igbvf: Intel(R) Gigabit Virtual Function Network Driver
[ 1.532749] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
[ 1.538826] sky2: driver version 1.30
[ 1.543025] usbcore: registered new device driver r8152-cfgselector
[ 1.549325] usbcore: registered new interface driver r8152
[ 1.555240] VFIO - User Level meta-driver version: 0.3
[ 1.563002] usbcore: registered new interface driver uas
[ 1.568365] usbcore: registered new interface driver usb-storage
[ 1.574444] usbcore: registered new interface driver usbserial_generic
[ 1.581001] usbserial: USB Serial support registered for generic
[ 1.587033] usbcore: registered new interface driver cp210x
[ 1.592632] usbserial: USB Serial support registered for cp210x
[ 1.598580] usbcore: registered new interface driver ftdi_sio
[ 1.604360] usbserial: USB Serial support registered for FTDI USB Serial Device
[ 1.611700] usbcore: registered new interface driver usb_serial_simple
[ 1.618256] usbserial: USB Serial support registered for carelink
[ 1.624380] usbserial: USB Serial support registered for flashloader
[ 1.630761] usbserial: USB Serial support registered for funsoft
[ 1.636793] usbserial: USB Serial support registered for google
[ 1.642740] usbserial: USB Serial support registered for hp4x
[ 1.648511] usbserial: USB Serial support registered for kaufmann
[ 1.654635] usbserial: USB Serial support registered for libtransistor
[ 1.661188] usbserial: USB Serial support registered for moto_modem
[ 1.667484] usbserial: USB Serial support registered for motorola_tetra
[ 1.674124] usbserial: USB Serial support registered for nokia
[ 1.679983] usbserial: USB Serial support registered for novatel_gps
[ 1.686365] usbserial: USB Serial support registered for siemens_mpi
[ 1.692745] usbserial: USB Serial support registered for suunto
[ 1.698701] usbserial: USB Serial support registered for vivopay
[ 1.704735] usbserial: USB Serial support registered for zio
[ 1.710428] usbcore: registered new interface driver usb_ehset_test
[ 1.719671] input: 30370000.snvs:snvs-powerkey as /devices/platform/soc@0/30000000.bus/30370000.snvs/30370000.snvs:snvs-powerkey/input/input0
[ 1.734449] snvs_rtc 30370000.snvs:snvs-rtc-lp: registered as rtc1
[ 1.740786] i2c_dev: i2c /dev entries driver
[ 1.746659] mx6s-csi 32e20000.csi1_bridge: initialising
[ 1.752803] mxc_mipi-csi 32e30000.mipi_csi: supply mipi-phy not found, using dummy regulator
[ 1.761536] mxc_mipi-csi 32e30000.mipi_csi: mipi csi v4l2 device registered
[ 1.768517] CSI: Registered sensor subdevice: mxc_mipi-csi.0
[ 1.774200] mxc_mipi-csi 32e30000.mipi_csi: lanes: 2, hs_settle: 13, clk_settle: 2, wclk: 1, freq: 333000000
[ 1.787691] Bluetooth: HCI UART driver ver 2.3
[ 1.792171] Bluetooth: HCI UART protocol H4 registered
[ 1.797320] Bluetooth: HCI UART protocol BCSP registered
[ 1.802659] Bluetooth: HCI UART protocol LL registered
[ 1.807805] Bluetooth: HCI UART protocol ATH3K registered
[ 1.813229] Bluetooth: HCI UART protocol Three-wire (H5) registered
[ 1.819595] Bluetooth: HCI UART protocol Broadcom registered
[ 1.825285] Bluetooth: HCI UART protocol QCA registered
[ 1.832051] sdhci: Secure Digital Host Controller Interface driver
[ 1.838258] sdhci: Copyright(c) Pierre Ossman
[ 1.843160] Synopsys Designware Multimedia Card Interface Driver
[ 1.849776] sdhci-pltfm: SDHCI platform and OF driver helper
[ 1.858027] ledtrig-cpu: registered to indicate activity on CPUs
[ 1.865468] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping ....
[ 1.872404] usbcore: registered new interface driver usbhid
[ 1.877988] usbhid: USB HID core driver
[ 1.886411] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
[ 1.888071] mmc2: SDHCI controller on 30b60000.mmc [30b60000.mmc] using ADMA
[ 1.904337] cs_system_cfg: CoreSight Configuration manager initialised
[ 1.911941] platform soc@0: Fixed dependency cycle(s) with /soc@0/bus@30000000/efuse@30350000
[ 1.923349] hantrodec 0 : module inserted. Major = 509
[ 1.929063] hantrodec 1 : module inserted. Major = 509
[ 1.935096] hx280enc: module inserted. Major <508>
[ 1.942556] NET: Registered PF_LLC protocol family
[ 1.947477] u32 classifier
[ 1.950232] input device check on
[ 1.953908] Actions configured
[ 1.957935] NET: Registered PF_INET6 protocol family
[ 1.964834] Segment Routing with IPv6
[ 1.965231] mmc2: new HS400 Enhanced strobe MMC card at address 0001
[ 1.968551] In-situ OAM (IOAM) with IPv6
[ 1.976133] mmcblk2: mmc2:0001 DG4008 7.28 GiB
[ 1.978869] NET: Registered PF_PACKET protocol family
[ 1.985205] mmcblk2boot0: mmc2:0001 DG4008 4.00 MiB
[ 1.988349] bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this.
[ 1.994285] mmcblk2boot1: mmc2:0001 DG4008 4.00 MiB
[ 2.007257] Bluetooth: RFCOMM TTY layer initialized
[ 2.012049] mmcblk2rpmb: mmc2:0001 DG4008 4.00 MiB, chardev (234:0)
[ 2.015938] Bluetooth: RFCOMM socket layer initialized
[ 2.027343] Bluetooth: RFCOMM ver 1.11
[ 2.031110] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[ 2.036428] Bluetooth: BNEP filters: protocol multicast
[ 2.041662] Bluetooth: BNEP socket layer initialized
[ 2.046633] Bluetooth: HIDP (Human Interface Emulation) ver 1.2
[ 2.052563] Bluetooth: HIDP socket layer initialized
[ 2.058703] 8021q: 802.1Q VLAN Support v1.8
[ 2.062927] lib80211: common routines for IEEE802.11 drivers
[ 2.068644] 9pnet: Installing 9P2000 support
[ 2.073074] Key type dns_resolver registered
[ 2.098561] registered taskstats version 1
[ 2.102942] Loading compiled-in X.509 certificates
[ 2.131329] gpio gpiochip0: Static allocation of GPIO base is deprecated, use dynamic allocation.
[ 2.142093] gpio gpiochip1: Static allocation of GPIO base is deprecated, use dynamic allocation.
[ 2.152588] gpio gpiochip2: Static allocation of GPIO base is deprecated, use dynamic allocation.
[ 2.163069] gpio gpiochip3: Static allocation of GPIO base is deprecated, use dynamic allocation.
[ 2.173556] gpio gpiochip4: Static allocation of GPIO base is deprecated, use dynamic allocation.
[ 2.185820] bt_regulator GPIO handle specifies active low - ignored
[ 2.186032] usb_phy_generic usbphynop1: dummy supplies not allowed for exclusive requests
[ 2.200592] usb_phy_generic usbphynop2: dummy supplies not allowed for exclusive requests
[ 2.209907] i2c i2c-0: IMX I2C adapter registered
[ 2.216025] rtc-pcf8523 1-0068: failed to set xtal load capacitance: -6
[ 2.224249] ov5640_mipi 1-003c: No sensor reset pin available
[ 2.226753] nxp-pca9450 0-0025: pca9450a probed.
[ 2.230058] ov5640_mipi 1-003c: supply DOVDD not found, using dummy regulator
[ 2.241915] ov5640_mipi 1-003c: supply DVDD not found, using dummy regulator
[ 2.249026] ov5640_mipi 1-003c: supply AVDD not found, using dummy regulator
[ 2.268878] ov5640_mipi 1-003c: Read reg error: reg=300a
[ 2.274204] ov5640_mipi 1-003c: Camera is not found
[ 2.279401] i2c i2c-1: IMX I2C adapter registered
[ 2.285694] i2c i2c-2: IMX I2C adapter registered
[ 2.292377] pwm_backlight_probe =================> entry
[ 2.293259] imx6q-pcie 33800000.pcie: host bridge /soc@0/pcie@33800000 ranges:
[ 2.298006] got pwm for backlight ------------<
[ 2.305063] imx6q-pcie 33800000.pcie: IO 0x001ff80000..0x001ff8ffff -> 0x0000000000
[ 2.310750] pwm backlight probe exit --------------------->
[ 2.317852] imx6q-pcie 33800000.pcie: MEM 0x0018000000..0x001fefffff -> 0x0018000000
[ 2.324483] jadard_dsi_probe entry -------->
[ 2.336307] samsung_dsim_host_attach entry ---------<>
[ 2.341552] drm_bridge_add =====>
[ 2.344966] samsung-dsim 32e10000.mipi_dsi: [drm:samsung_dsim_host_attach] Attached display-8hd-a device
[ 2.352990] phy phy-32f00000.pcie-phy.0: phy poweron failed --> -110
[ 2.354478] drm_bridge_add =====>
[ 2.360823] imx6q-pcie 33800000.pcie: waiting for PHY ready timeout!
[ 2.364224] samsung_dsim_host_attach: before filling dsi->lanes, format info ===>
[ 2.370637] imx6q-pcie: probe of 33800000.pcie failed with error -110
[ 2.378146] samsung_dsim_host_attach exit -------->
[ 2.378146]
[ 2.378149] jadard_dsi_probe exit -------->
[ 2.397445] pps pps0: new PPS source ptp0
[ 2.405055] fec 30be0000.ethernet eth0: registered PHC device 0
[ 2.411975] imx_usb 32e40000.usb: No over current polarity defined
[ 2.421358] ci_hdrc ci_hdrc.0: EHCI Host Controller
[ 2.426274] ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
[ 2.448046] ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
[ 2.456938] hub 1-0:1.0: USB hub found
[ 2.461040] hub 1-0:1.0: 1 port detected
[ 2.466355] imx_usb 32e50000.usb: No over current polarity defined
[ 2.475670] ci_hdrc ci_hdrc.1: EHCI Host Controller
[ 2.480582] ci_hdrc ci_hdrc.1: new USB bus registered, assigned bus number 2
[ 2.500050] ci_hdrc ci_hdrc.1: USB 2.0 started, EHCI 1.00
[ 2.506388] hub 2-0:1.0: USB hub found
[ 2.510171] hub 2-0:1.0: 1 port detected
[ 2.515876] imx-cpufreq-dt imx-cpufreq-dt: cpu speed grade 2 mkt segment 2 supported-hw 0x4 0x4
[ 2.528305] sdhci-esdhc-imx 30b40000.mmc: Got CD GPIO
[ 2.529102] galcore: clk_get vg clock failed, disable vg!
[ 2.539344] Galcore version 6.4.11.p2.745085
[ 2.566035] mmc0: SDHCI controller on 30b40000.mmc [30b40000.mmc] using ADMA
[ 2.589012] [drm] Initialized vivante 1.0.0 20170808 for 38000000.gpu on minor 0
[ 2.605239] mmc0: host does not support reading read-only switch, assuming write-enable
[ 2.615263] mmc0: new high speed SDHC card at address b368
[ 2.621932] mmcblk0: mmc0:b368 USD 7.47 GiB
[ 2.628209] mmcblk0: p1 p2
[ 2.637683] mmc1: SDHCI controller on 30b50000.mmc [30b50000.mmc] using ADMA
[ 2.648504] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[ 2.658234] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[ 2.664524] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
[ 2.671811] clk: Disabling unused clocks
[ 2.675818] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
[ 2.682392] ALSA device list:
[ 2.684447] platform regulatory.0: Falling back to sysfs fallback for: regulatory.db
[ 2.687411] No soundcards found.
[ 2.850499] EXT4-fs (mmcblk0p2): mounted filesystem 9f1b4de1-6b40-42f9-b71b-940c68df912c r/w with ordered data mode. Quota mode: none.
[ 2.862791] VFS: Mounted root (ext4 filesystem) on device 179:98.
[ 2.869680] devtmpfs: mounted
[ 2.873515] Freeing unused kernel memory: 3968K
[ 2.878122] Run /sbin/init as init process
[ 3.485071] systemd[1]: System time before build time, advancing clock.
[ 3.632804] systemd[1]: systemd 255.4^ running in system mode (+PAM -AUDIT -SELINUX -APPARMOR +IMA -SMACK +SECCOMP -GCRYPT -GNUTLS -OPENSSL +ACL +BLKID -CURL -ELFUTILS -FIDO2 -IDN2 -IDN -IPTC +KMOD -LIBCRYPTSETUP +LIBFDISK -PCRE2 -PWQUALITY -P11KIT -QRENCODE -TPM2 -BZIP2 -LZ4 -XZ -ZLIB +ZSTD -BPF_FRAMEWORK +XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
[ 3.664660] systemd[1]: Detected architecture arm64.

Welcome to NXP i.MX Release Distro 6.6-scarthgap (scarthgap)!

Attachment: imx8mm-jd9365da-mipi-dsi.dts
Description: Binary data

// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 Radxa Limited
* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
*
* Author:
* - Jagan Teki <jagan@xxxxxxxxxxxxxxxxxxxx>
* - Stephen Chen <stephen@xxxxxxxxx>
*/

#include <drm/drm_mipi_dsi.h>
#include <drm/drm_modes.h>
#include <drm/drm_panel.h>
#include <drm/drm_print.h>

#include <linux/gpio/consumer.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regulator/consumer.h>

#define JD9365DA_INIT_CMD_LEN 2

struct jadard_init_cmd {
u8 data[JD9365DA_INIT_CMD_LEN];
};

struct jadard_panel_desc {
const struct drm_display_mode mode;
unsigned int lanes;
enum mipi_dsi_pixel_format format;
const struct jadard_init_cmd *init_cmds;
u32 num_init_cmds;
};

struct jadard {
struct drm_panel panel;
struct mipi_dsi_device *dsi;
const struct jadard_panel_desc *desc;

struct regulator *vdd;
struct regulator *vccio;
struct gpio_desc *reset;
};

static inline struct jadard *panel_to_jadard(struct drm_panel *panel)
{
return container_of(panel, struct jadard, panel);
}

static int jadard_enable(struct drm_panel *panel)
{
struct device *dev = panel->dev;
struct jadard *jadard = panel_to_jadard(panel);
const struct jadard_panel_desc *desc = jadard->desc;
struct mipi_dsi_device *dsi = jadard->dsi;
unsigned int i;
int err;

pr_info("jadard_enable entry --------> \n");
msleep(10);

for (i = 0; i < desc->num_init_cmds; i++) {
const struct jadard_init_cmd *cmd = &desc->init_cmds[i];

err = mipi_dsi_dcs_write_buffer(dsi, cmd->data, JD9365DA_INIT_CMD_LEN);
if (err < 0)
return err;
pr_info("written to jd9365da ic registers=======> \n");
}

msleep(120);

err = mipi_dsi_dcs_exit_sleep_mode(dsi);
if (err < 0)
DRM_DEV_ERROR(dev, "failed to exit sleep mode ret = %d\n", err);

err = mipi_dsi_dcs_set_display_on(dsi);
if (err < 0)
DRM_DEV_ERROR(dev, "failed to set display on ret = %d\n", err);

pr_info("jadard_enable exit --------> \n");
return 0;
}

static int jadard_disable(struct drm_panel *panel)
{
struct device *dev = panel->dev;
struct jadard *jadard = panel_to_jadard(panel);
int ret;

ret = mipi_dsi_dcs_set_display_off(jadard->dsi);
if (ret < 0)
DRM_DEV_ERROR(dev, "failed to set display off: %d\n", ret);

ret = mipi_dsi_dcs_enter_sleep_mode(jadard->dsi);
if (ret < 0)
DRM_DEV_ERROR(dev, "failed to enter sleep mode: %d\n", ret);

return 0;
}

static int jadard_prepare(struct drm_panel *panel)
{
struct jadard *jadard = panel_to_jadard(panel);
int ret;

pr_info("jadard_prepare entry ========> \n ");
ret = regulator_enable(jadard->vccio);
if (ret)
return ret;

ret = regulator_enable(jadard->vdd);
if (ret)
return ret;

gpiod_set_value(jadard->reset, 1);
msleep(5);

gpiod_set_value(jadard->reset, 0);
msleep(10);

gpiod_set_value(jadard->reset, 1);
msleep(120);

pr_info("jadard_prepare exit ========> \n ");
return 0;
}

static int jadard_unprepare(struct drm_panel *panel)
{
struct jadard *jadard = panel_to_jadard(panel);

gpiod_set_value(jadard->reset, 1);
msleep(120);

regulator_disable(jadard->vdd);
regulator_disable(jadard->vccio);

return 0;
}

static int jadard_get_modes(struct drm_panel *panel,
struct drm_connector *connector)
{
struct jadard *jadard = panel_to_jadard(panel);
const struct drm_display_mode *desc_mode = &jadard->desc->mode;
struct drm_display_mode *mode;

mode = drm_mode_duplicate(connector->dev, desc_mode);
if (!mode) {
DRM_DEV_ERROR(&jadard->dsi->dev, "failed to add mode %ux%ux@%u\n",
desc_mode->hdisplay, desc_mode->vdisplay,
drm_mode_vrefresh(desc_mode));
return -ENOMEM;
}

drm_mode_set_name(mode);
drm_mode_probed_add(connector, mode);

connector->display_info.width_mm = mode->width_mm;
connector->display_info.height_mm = mode->height_mm;

return 1;
}

static const struct drm_panel_funcs jadard_funcs = {
.disable = jadard_disable,
.unprepare = jadard_unprepare,
.prepare = jadard_prepare,
.enable = jadard_enable,
.get_modes = jadard_get_modes,
};

static const struct jadard_init_cmd radxa_display_8hd_ad002_init_cmds[] = {
{ .data = { 0xE0, 0x00 } },
{ .data = { 0xE1, 0x93 } },
{ .data = { 0xE2, 0x65 } },
{ .data = { 0xE3, 0xF8 } },
{ .data = { 0x80, 0x03 } },
{ .data = { 0xE0, 0x01 } },
{ .data = { 0x00, 0x00 } },
{ .data = { 0x01, 0x7E } },
{ .data = { 0x03, 0x00 } },
{ .data = { 0x04, 0x65 } },
{ .data = { 0x0C, 0x74 } },
{ .data = { 0x17, 0x00 } },
{ .data = { 0x18, 0xB7 } },
{ .data = { 0x19, 0x00 } },
{ .data = { 0x1A, 0x00 } },
{ .data = { 0x1B, 0xB7 } },
{ .data = { 0x1C, 0x00 } },
{ .data = { 0x24, 0xFE } },
{ .data = { 0x37, 0x19 } },
{ .data = { 0x38, 0x05 } },
{ .data = { 0x39, 0x00 } },
{ .data = { 0x3A, 0x01 } },
{ .data = { 0x3B, 0x01 } },
{ .data = { 0x3C, 0x70 } },
{ .data = { 0x3D, 0xFF } },
{ .data = { 0x3E, 0xFF } },
{ .data = { 0x3F, 0xFF } },
{ .data = { 0x40, 0x06 } },
{ .data = { 0x41, 0xA0 } },
{ .data = { 0x43, 0x1E } },
{ .data = { 0x44, 0x0F } },
{ .data = { 0x45, 0x28 } },
{ .data = { 0x4B, 0x04 } },
{ .data = { 0x55, 0x02 } },
{ .data = { 0x56, 0x01 } },
{ .data = { 0x57, 0xA9 } },
{ .data = { 0x58, 0x0A } },
{ .data = { 0x59, 0x0A } },
{ .data = { 0x5A, 0x37 } },
{ .data = { 0x5B, 0x19 } },
{ .data = { 0x5D, 0x78 } },
{ .data = { 0x5E, 0x63 } },
{ .data = { 0x5F, 0x54 } },
{ .data = { 0x60, 0x49 } },
{ .data = { 0x61, 0x45 } },
{ .data = { 0x62, 0x38 } },
{ .data = { 0x63, 0x3D } },
{ .data = { 0x64, 0x28 } },
{ .data = { 0x65, 0x43 } },
{ .data = { 0x66, 0x41 } },
{ .data = { 0x67, 0x43 } },
{ .data = { 0x68, 0x62 } },
{ .data = { 0x69, 0x50 } },
{ .data = { 0x6A, 0x57 } },
{ .data = { 0x6B, 0x49 } },
{ .data = { 0x6C, 0x44 } },
{ .data = { 0x6D, 0x37 } },
{ .data = { 0x6E, 0x23 } },
{ .data = { 0x6F, 0x10 } },
{ .data = { 0x70, 0x78 } },
{ .data = { 0x71, 0x63 } },
{ .data = { 0x72, 0x54 } },
{ .data = { 0x73, 0x49 } },
{ .data = { 0x74, 0x45 } },
{ .data = { 0x75, 0x38 } },
{ .data = { 0x76, 0x3D } },
{ .data = { 0x77, 0x28 } },
{ .data = { 0x78, 0x43 } },
{ .data = { 0x79, 0x41 } },
{ .data = { 0x7A, 0x43 } },
{ .data = { 0x7B, 0x62 } },
{ .data = { 0x7C, 0x50 } },
{ .data = { 0x7D, 0x57 } },
{ .data = { 0x7E, 0x49 } },
{ .data = { 0x7F, 0x44 } },
{ .data = { 0x80, 0x37 } },
{ .data = { 0x81, 0x23 } },
{ .data = { 0x82, 0x10 } },
{ .data = { 0xE0, 0x02 } },
{ .data = { 0x00, 0x47 } },
{ .data = { 0x01, 0x47 } },
{ .data = { 0x02, 0x45 } },
{ .data = { 0x03, 0x45 } },
{ .data = { 0x04, 0x4B } },
{ .data = { 0x05, 0x4B } },
{ .data = { 0x06, 0x49 } },
{ .data = { 0x07, 0x49 } },
{ .data = { 0x08, 0x41 } },
{ .data = { 0x09, 0x1F } },
{ .data = { 0x0A, 0x1F } },
{ .data = { 0x0B, 0x1F } },
{ .data = { 0x0C, 0x1F } },
{ .data = { 0x0D, 0x1F } },
{ .data = { 0x0E, 0x1F } },
{ .data = { 0x0F, 0x5F } },
{ .data = { 0x10, 0x5F } },
{ .data = { 0x11, 0x57 } },
{ .data = { 0x12, 0x77 } },
{ .data = { 0x13, 0x35 } },
{ .data = { 0x14, 0x1F } },
{ .data = { 0x15, 0x1F } },
{ .data = { 0x16, 0x46 } },
{ .data = { 0x17, 0x46 } },
{ .data = { 0x18, 0x44 } },
{ .data = { 0x19, 0x44 } },
{ .data = { 0x1A, 0x4A } },
{ .data = { 0x1B, 0x4A } },
{ .data = { 0x1C, 0x48 } },
{ .data = { 0x1D, 0x48 } },
{ .data = { 0x1E, 0x40 } },
{ .data = { 0x1F, 0x1F } },
{ .data = { 0x20, 0x1F } },
{ .data = { 0x21, 0x1F } },
{ .data = { 0x22, 0x1F } },
{ .data = { 0x23, 0x1F } },
{ .data = { 0x24, 0x1F } },
{ .data = { 0x25, 0x5F } },
{ .data = { 0x26, 0x5F } },
{ .data = { 0x27, 0x57 } },
{ .data = { 0x28, 0x77 } },
{ .data = { 0x29, 0x35 } },
{ .data = { 0x2A, 0x1F } },
{ .data = { 0x2B, 0x1F } },
{ .data = { 0x58, 0x40 } },
{ .data = { 0x59, 0x00 } },
{ .data = { 0x5A, 0x00 } },
{ .data = { 0x5B, 0x10 } },
{ .data = { 0x5C, 0x06 } },
{ .data = { 0x5D, 0x40 } },
{ .data = { 0x5E, 0x01 } },
{ .data = { 0x5F, 0x02 } },
{ .data = { 0x60, 0x30 } },
{ .data = { 0x61, 0x01 } },
{ .data = { 0x62, 0x02 } },
{ .data = { 0x63, 0x03 } },
{ .data = { 0x64, 0x6B } },
{ .data = { 0x65, 0x05 } },
{ .data = { 0x66, 0x0C } },
{ .data = { 0x67, 0x73 } },
{ .data = { 0x68, 0x09 } },
{ .data = { 0x69, 0x03 } },
{ .data = { 0x6A, 0x56 } },
{ .data = { 0x6B, 0x08 } },
{ .data = { 0x6C, 0x00 } },
{ .data = { 0x6D, 0x04 } },
{ .data = { 0x6E, 0x04 } },
{ .data = { 0x6F, 0x88 } },
{ .data = { 0x70, 0x00 } },
{ .data = { 0x71, 0x00 } },
{ .data = { 0x72, 0x06 } },
{ .data = { 0x73, 0x7B } },
{ .data = { 0x74, 0x00 } },
{ .data = { 0x75, 0xF8 } },
{ .data = { 0x76, 0x00 } },
{ .data = { 0x77, 0xD5 } },
{ .data = { 0x78, 0x2E } },
{ .data = { 0x79, 0x12 } },
{ .data = { 0x7A, 0x03 } },
{ .data = { 0x7B, 0x00 } },
{ .data = { 0x7C, 0x00 } },
{ .data = { 0x7D, 0x03 } },
{ .data = { 0x7E, 0x7B } },
{ .data = { 0xE0, 0x04 } },
{ .data = { 0x00, 0x0E } },
{ .data = { 0x02, 0xB3 } },
{ .data = { 0x09, 0x60 } },
{ .data = { 0x0E, 0x2A } },
{ .data = { 0x36, 0x59 } },
{ .data = { 0xE0, 0x00 } },
};

static const struct jadard_panel_desc radxa_display_8hd_ad002_desc = {
.mode = {
.clock = 70000,

.hdisplay = 800,
.hsync_start = 800 + 40,
.hsync_end = 800 + 40 + 18,
.htotal = 800 + 40 + 18 + 20,

.vdisplay = 1280,
.vsync_start = 1280 + 20,
.vsync_end = 1280 + 20 + 4,
.vtotal = 1280 + 20 + 4 + 20,

.width_mm = 127,
.height_mm = 199,
.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
},
.lanes = 4,
.format = MIPI_DSI_FMT_RGB888,
.init_cmds = radxa_display_8hd_ad002_init_cmds,
.num_init_cmds = ARRAY_SIZE(radxa_display_8hd_ad002_init_cmds),
};

static const struct jadard_init_cmd cz101b4001_init_cmds[] = {
{ .data = { 0xE0, 0x00 } },
{ .data = { 0xE1, 0x93 } },
{ .data = { 0xE2, 0x65 } },
{ .data = { 0xE3, 0xF8 } },
{ .data = { 0x80, 0x03 } },
{ .data = { 0xE0, 0x01 } },
{ .data = { 0x00, 0x00 } },
{ .data = { 0x01, 0x3B } },
{ .data = { 0x0C, 0x74 } },
{ .data = { 0x17, 0x00 } },
{ .data = { 0x18, 0xAF } },
{ .data = { 0x19, 0x00 } },
{ .data = { 0x1A, 0x00 } },
{ .data = { 0x1B, 0xAF } },
{ .data = { 0x1C, 0x00 } },
{ .data = { 0x35, 0x26 } },
{ .data = { 0x37, 0x09 } },
{ .data = { 0x38, 0x04 } },
{ .data = { 0x39, 0x00 } },
{ .data = { 0x3A, 0x01 } },
{ .data = { 0x3C, 0x78 } },
{ .data = { 0x3D, 0xFF } },
{ .data = { 0x3E, 0xFF } },
{ .data = { 0x3F, 0x7F } },
{ .data = { 0x40, 0x06 } },
{ .data = { 0x41, 0xA0 } },
{ .data = { 0x42, 0x81 } },
{ .data = { 0x43, 0x14 } },
{ .data = { 0x44, 0x23 } },
{ .data = { 0x45, 0x28 } },
{ .data = { 0x55, 0x02 } },
{ .data = { 0x57, 0x69 } },
{ .data = { 0x59, 0x0A } },
{ .data = { 0x5A, 0x2A } },
{ .data = { 0x5B, 0x17 } },
{ .data = { 0x5D, 0x7F } },
{ .data = { 0x5E, 0x6B } },
{ .data = { 0x5F, 0x5C } },
{ .data = { 0x60, 0x4F } },
{ .data = { 0x61, 0x4D } },
{ .data = { 0x62, 0x3F } },
{ .data = { 0x63, 0x42 } },
{ .data = { 0x64, 0x2B } },
{ .data = { 0x65, 0x44 } },
{ .data = { 0x66, 0x43 } },
{ .data = { 0x67, 0x43 } },
{ .data = { 0x68, 0x63 } },
{ .data = { 0x69, 0x52 } },
{ .data = { 0x6A, 0x5A } },
{ .data = { 0x6B, 0x4F } },
{ .data = { 0x6C, 0x4E } },
{ .data = { 0x6D, 0x20 } },
{ .data = { 0x6E, 0x0F } },
{ .data = { 0x6F, 0x00 } },
{ .data = { 0x70, 0x7F } },
{ .data = { 0x71, 0x6B } },
{ .data = { 0x72, 0x5C } },
{ .data = { 0x73, 0x4F } },
{ .data = { 0x74, 0x4D } },
{ .data = { 0x75, 0x3F } },
{ .data = { 0x76, 0x42 } },
{ .data = { 0x77, 0x2B } },
{ .data = { 0x78, 0x44 } },
{ .data = { 0x79, 0x43 } },
{ .data = { 0x7A, 0x43 } },
{ .data = { 0x7B, 0x63 } },
{ .data = { 0x7C, 0x52 } },
{ .data = { 0x7D, 0x5A } },
{ .data = { 0x7E, 0x4F } },
{ .data = { 0x7F, 0x4E } },
{ .data = { 0x80, 0x20 } },
{ .data = { 0x81, 0x0F } },
{ .data = { 0x82, 0x00 } },
{ .data = { 0xE0, 0x02 } },
{ .data = { 0x00, 0x02 } },
{ .data = { 0x01, 0x02 } },
{ .data = { 0x02, 0x00 } },
{ .data = { 0x03, 0x00 } },
{ .data = { 0x04, 0x1E } },
{ .data = { 0x05, 0x1E } },
{ .data = { 0x06, 0x1F } },
{ .data = { 0x07, 0x1F } },
{ .data = { 0x08, 0x1F } },
{ .data = { 0x09, 0x17 } },
{ .data = { 0x0A, 0x17 } },
{ .data = { 0x0B, 0x37 } },
{ .data = { 0x0C, 0x37 } },
{ .data = { 0x0D, 0x47 } },
{ .data = { 0x0E, 0x47 } },
{ .data = { 0x0F, 0x45 } },
{ .data = { 0x10, 0x45 } },
{ .data = { 0x11, 0x4B } },
{ .data = { 0x12, 0x4B } },
{ .data = { 0x13, 0x49 } },
{ .data = { 0x14, 0x49 } },
{ .data = { 0x15, 0x1F } },
{ .data = { 0x16, 0x01 } },
{ .data = { 0x17, 0x01 } },
{ .data = { 0x18, 0x00 } },
{ .data = { 0x19, 0x00 } },
{ .data = { 0x1A, 0x1E } },
{ .data = { 0x1B, 0x1E } },
{ .data = { 0x1C, 0x1F } },
{ .data = { 0x1D, 0x1F } },
{ .data = { 0x1E, 0x1F } },
{ .data = { 0x1F, 0x17 } },
{ .data = { 0x20, 0x17 } },
{ .data = { 0x21, 0x37 } },
{ .data = { 0x22, 0x37 } },
{ .data = { 0x23, 0x46 } },
{ .data = { 0x24, 0x46 } },
{ .data = { 0x25, 0x44 } },
{ .data = { 0x26, 0x44 } },
{ .data = { 0x27, 0x4A } },
{ .data = { 0x28, 0x4A } },
{ .data = { 0x29, 0x48 } },
{ .data = { 0x2A, 0x48 } },
{ .data = { 0x2B, 0x1F } },
{ .data = { 0x2C, 0x01 } },
{ .data = { 0x2D, 0x01 } },
{ .data = { 0x2E, 0x00 } },
{ .data = { 0x2F, 0x00 } },
{ .data = { 0x30, 0x1F } },
{ .data = { 0x31, 0x1F } },
{ .data = { 0x32, 0x1E } },
{ .data = { 0x33, 0x1E } },
{ .data = { 0x34, 0x1F } },
{ .data = { 0x35, 0x17 } },
{ .data = { 0x36, 0x17 } },
{ .data = { 0x37, 0x37 } },
{ .data = { 0x38, 0x37 } },
{ .data = { 0x39, 0x08 } },
{ .data = { 0x3A, 0x08 } },
{ .data = { 0x3B, 0x0A } },
{ .data = { 0x3C, 0x0A } },
{ .data = { 0x3D, 0x04 } },
{ .data = { 0x3E, 0x04 } },
{ .data = { 0x3F, 0x06 } },
{ .data = { 0x40, 0x06 } },
{ .data = { 0x41, 0x1F } },
{ .data = { 0x42, 0x02 } },
{ .data = { 0x43, 0x02 } },
{ .data = { 0x44, 0x00 } },
{ .data = { 0x45, 0x00 } },
{ .data = { 0x46, 0x1F } },
{ .data = { 0x47, 0x1F } },
{ .data = { 0x48, 0x1E } },
{ .data = { 0x49, 0x1E } },
{ .data = { 0x4A, 0x1F } },
{ .data = { 0x4B, 0x17 } },
{ .data = { 0x4C, 0x17 } },
{ .data = { 0x4D, 0x37 } },
{ .data = { 0x4E, 0x37 } },
{ .data = { 0x4F, 0x09 } },
{ .data = { 0x50, 0x09 } },
{ .data = { 0x51, 0x0B } },
{ .data = { 0x52, 0x0B } },
{ .data = { 0x53, 0x05 } },
{ .data = { 0x54, 0x05 } },
{ .data = { 0x55, 0x07 } },
{ .data = { 0x56, 0x07 } },
{ .data = { 0x57, 0x1F } },
{ .data = { 0x58, 0x40 } },
{ .data = { 0x5B, 0x30 } },
{ .data = { 0x5C, 0x16 } },
{ .data = { 0x5D, 0x34 } },
{ .data = { 0x5E, 0x05 } },
{ .data = { 0x5F, 0x02 } },
{ .data = { 0x63, 0x00 } },
{ .data = { 0x64, 0x6A } },
{ .data = { 0x67, 0x73 } },
{ .data = { 0x68, 0x1D } },
{ .data = { 0x69, 0x08 } },
{ .data = { 0x6A, 0x6A } },
{ .data = { 0x6B, 0x08 } },
{ .data = { 0x6C, 0x00 } },
{ .data = { 0x6D, 0x00 } },
{ .data = { 0x6E, 0x00 } },
{ .data = { 0x6F, 0x88 } },
{ .data = { 0x75, 0xFF } },
{ .data = { 0x77, 0xDD } },
{ .data = { 0x78, 0x3F } },
{ .data = { 0x79, 0x15 } },
{ .data = { 0x7A, 0x17 } },
{ .data = { 0x7D, 0x14 } },
{ .data = { 0x7E, 0x82 } },
{ .data = { 0xE0, 0x04 } },
{ .data = { 0x00, 0x0E } },
{ .data = { 0x02, 0xB3 } },
{ .data = { 0x09, 0x61 } },
{ .data = { 0x0E, 0x48 } },
{ .data = { 0xE0, 0x00 } },
{ .data = { 0xE6, 0x02 } },
{ .data = { 0xE7, 0x0C } },
};

static const struct jadard_panel_desc cz101b4001_desc = {
.mode = {
.clock = 70000,

.hdisplay = 800,
.hsync_start = 800 + 40,
.hsync_end = 800 + 40 + 18,
.htotal = 800 + 40 + 18 + 20,

.vdisplay = 1280,
.vsync_start = 1280 + 20,
.vsync_end = 1280 + 20 + 4,
.vtotal = 1280 + 20 + 4 + 20,

.width_mm = 62,
.height_mm = 110,
.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
},
.lanes = 4,
.format = MIPI_DSI_FMT_RGB888,
.init_cmds = cz101b4001_init_cmds,
.num_init_cmds = ARRAY_SIZE(cz101b4001_init_cmds),
};

static const struct jadard_init_cmd imx8mm_display_8hd_a_init_cmds[] = {
{ .data = { 0xE0, 0x00 } },
{ .data = { 0xE1, 0x93 } },
{ .data = { 0xE2, 0x65 } },
{ .data = { 0xE3, 0xF8 } },
{ .data = { 0x80, 0x03 } },
{ .data = { 0xE0, 0x01 } },
{ .data = { 0x03, 0x00 } },
{ .data = { 0x04, 0x2F } },

{ .data = { 0x17, 0x10 } },
{ .data = { 0x18, 0x0F } },
{ .data = { 0x19, 0x01 } },
{ .data = { 0x1A, 0x10 } },
{ .data = { 0x1B, 0x0F } },
{ .data = { 0x1C, 0x01 } },

{ .data = { 0x24, 0xFE} },
{ .data = { 0x25, 0x20} },

{ .data = { 0x35, 0x23} },

{ .data = { 0x37, 0x09} },

{ .data = { 0x38, 0x04} },
{ .data = { 0x39, 0x08} },
{ .data = { 0x3A, 0x12} },
{ .data = { 0x3C, 0x78} },
{ .data = { 0x3D, 0xFF} },
{ .data = { 0x3E, 0xFF} },
{ .data = { 0x3F, 0xFF} },

{ .data = { 0x40, 0x06} },
{ .data = { 0x41, 0xA0} },
{ .data = { 0x43, 0x14} },
{ .data = { 0x44, 0x0F} },
{ .data = { 0x45, 0x30} },
{ .data = { 0x4B, 0x04} },

{ .data = { 0x55, 0x0F} },
{ .data = { 0x57, 0x65} },
{ .data = { 0x59, 0x0A} },
{ .data = { 0x5A, 0x28} },
{ .data = { 0x5B, 0x0F} },
//--- Gamma2.2 20200710 ----//

{ .data = { 0x5D, 0x7C} },
{ .data = { 0x5E, 0x68} },
{ .data = { 0x5F, 0x58} },
{ .data = { 0x60, 0x4B} },
{ .data = { 0x61, 0x45} },
{ .data = { 0x62, 0x35} },
{ .data = { 0x63, 0x38} },
{ .data = { 0x64, 0x20} },
{ .data = { 0x65, 0x38} },
{ .data = { 0x66, 0x35} },
{ .data = { 0x67, 0x34} },
{ .data = { 0x68, 0x4E} },
{ .data = { 0x69, 0x38} },
{ .data = { 0x6A, 0x3D} },
{ .data = { 0x6B, 0x2E} },
{ .data = { 0x6C, 0x2B} },
{ .data = { 0x6D, 0x20} },
{ .data = { 0x6E, 0x13} },
{ .data = { 0x6F, 0x0C} },
{ .data = { 0x70, 0x7C} },
{ .data = { 0x71, 0x68} },
{ .data = { 0x72, 0x58} },
{ .data = { 0x73, 0x4B} },
{ .data = { 0x74, 0x45} },
{ .data = { 0x75, 0x35} },
{ .data = { 0x76, 0x38} },
{ .data = { 0x77, 0x20} },
{ .data = { 0x78, 0x38} },
{ .data = { 0x79, 0x35} },
{ .data = { 0x7A, 0x34} },
{ .data = { 0x7B, 0x4E} },
{ .data = { 0x7C, 0x38} },
{ .data = { 0x7D, 0x3D} },
{ .data = { 0x7E, 0x2E} },
{ .data = { 0x7F, 0x2B} },
{ .data = { 0x80, 0x20} },
{ .data = { 0x81, 0x13} },
{ .data = { 0x82, 0x0C} },
//--- Gamma2.2 end ----//

{ .data = { 0xE0, 0x02} },

{ .data = { 0x00, 0x5E} },
{ .data = { 0x01, 0x5F} },
{ .data = { 0x02, 0x57} },
{ .data = { 0x03, 0x58} },
{ .data = { 0x04, 0x44} },
{ .data = { 0x05, 0x46} },
{ .data = { 0x06, 0x48} },
{ .data = { 0x07, 0x4A} },
{ .data = { 0x08, 0x40} },
{ .data = { 0x09, 0x5F} },
{ .data = { 0x0A, 0x5F} },
{ .data = { 0x0B, 0x5F} },
{ .data = { 0x0C, 0x5F} },
{ .data = { 0x0D, 0x5F} },
{ .data = { 0x0E, 0x5F} },
{ .data = { 0x0F, 0x50} },
{ .data = { 0x10, 0x5F} },
{ .data = { 0x11, 0x5F} },
{ .data = { 0x12, 0x5F} },
{ .data = { 0x13, 0x5F} },
{ .data = { 0x14, 0x5F} },
{ .data = { 0x15, 0x5F} },

{ .data = { 0x16, 0x5E} },
{ .data = { 0x17, 0x5F} },
{ .data = { 0x18, 0x57} },
{ .data = { 0x19, 0x58} },
{ .data = { 0x1A, 0x45} },
{ .data = { 0x1B, 0x47} },
{ .data = { 0x1C, 0x49} },
{ .data = { 0x1D, 0x4B} },
{ .data = { 0x1E, 0x41} },
{ .data = { 0x1F, 0x5F} },
{ .data = { 0x20, 0x5F} },
{ .data = { 0x21, 0x5F} },
{ .data = { 0x22, 0x5F} },
{ .data = { 0x23, 0x5F} },
{ .data = { 0x24, 0x5F} },
{ .data = { 0x25, 0x51} },
{ .data = { 0x26, 0x5F} },
{ .data = { 0x27, 0x5F} },
{ .data = { 0x28, 0x5F} },
{ .data = { 0x29, 0x5F} },
{ .data = { 0x2A, 0x5F} },
{ .data = { 0x2B, 0x5F} },
{ .data = { 0x2C, 0x1F} },
{ .data = { 0x2D, 0x1E} },
{ .data = { 0x2E, 0x17} },
{ .data = { 0x2F, 0x18} },
{ .data = { 0x30, 0x0B} },
{ .data = { 0x31, 0x09} },
{ .data = { 0x32, 0x07} },
{ .data = { 0x33, 0x05} },
{ .data = { 0x34, 0x11} },
{ .data = { 0x35, 0x1F} },
{ .data = { 0x36, 0x1F} },
{ .data = { 0x37, 0x1F} },
{ .data = { 0x38, 0x1F} },
{ .data = { 0x39, 0x1F} },
{ .data = { 0x3A, 0x1F} },
{ .data = { 0x3B, 0x01} },
{ .data = { 0x3C, 0x1F} },
{ .data = { 0x3D, 0x1F} },
{ .data = { 0x3E, 0x1F} },
{ .data = { 0x3F, 0x1F} },
{ .data = { 0x40, 0x1F} },
{ .data = { 0x41, 0x1F} },

{ .data = { 0x42, 0x1F} },
{ .data = { 0x43, 0x1E} },
{ .data = { 0x44, 0x17} },
{ .data = { 0x45, 0x18} },
{ .data = { 0x46, 0x0A} },
{ .data = { 0x47, 0x08} },
{ .data = { 0x48, 0x06} },
{ .data = { 0x49, 0x04} },
{ .data = { 0x4A, 0x10} },
{ .data = { 0x4B, 0x1F} },
{ .data = { 0x4C, 0x1F} },
{ .data = { 0x4D, 0x1F} },
{ .data = { 0x4E, 0x1F} },
{ .data = { 0x4F, 0x1F} },
{ .data = { 0x50, 0x1F} },
{ .data = { 0x51, 0x00} },
{ .data = { 0x52, 0x1F} },
{ .data = { 0x53, 0x1F} },
{ .data = { 0x54, 0x1F} },
{ .data = { 0x55, 0x1F} },
{ .data = { 0x56, 0x1F} },
{ .data = { 0x57, 0x1F} },
{ .data = { 0x58, 0x40} },
{ .data = { 0x59, 0x00} },
{ .data = { 0x5A, 0x00} },
{ .data = { 0x5B, 0x30} },
{ .data = { 0x5C, 0x0B} },
{ .data = { 0x5D, 0x30} },
{ .data = { 0x5E, 0x01} },
{ .data = { 0x5F, 0x02} },
{ .data = { 0x60, 0x30} },
{ .data = { 0x61, 0x03} },
{ .data = { 0x62, 0x04} },
{ .data = { 0x63, 0x1C} },
{ .data = { 0x64, 0x6A} },
{ .data = { 0x65, 0x75} },
{ .data = { 0x66, 0x0F} },
{ .data = { 0x67, 0x73} },
{ .data = { 0x68, 0x0D} },
{ .data = { 0x69, 0x1C} },
{ .data = { 0x6A, 0x6A} },
{ .data = { 0x6B, 0x00} },
{ .data = { 0x6C, 0x00} },
{ .data = { 0x6D, 0x00} },
{ .data = { 0x6E, 0x00} },
{ .data = { 0x6F, 0x88} },
{ .data = { 0x70, 0x00} },
{ .data = { 0x71, 0x00} },
{ .data = { 0x72, 0x06} },
{ .data = { 0x73, 0x7B} },
{ .data = { 0x74, 0x00} },
{ .data = { 0x75, 0xBB} },
{ .data = { 0x76, 0x01} },
{ .data = { 0x77, 0x0D} },
{ .data = { 0x78, 0x24} },
{ .data = { 0x79, 0x00} },
{ .data = { 0x7A, 0x00} },
{ .data = { 0x7B, 0x00} },
{ .data = { 0x7C, 0x00} },
{ .data = { 0x7D, 0x03} },
{ .data = { 0x7E, 0x7B} },

{ .data = { 0xE0, 0x04} },
{ .data = { 0x00, 0x0E} },
{ .data = { 0x02, 0xB3} },
{ .data = { 0x09, 0x60} },
{ .data = { 0x0E, 0x48} },
{ .data = { 0xE0, 0x00} },
};

static const struct jadard_panel_desc imx8mm_display_8hd_a_desc = {
.mode = {
.clock = 70000,

.hdisplay = 800,
.hsync_start = 800 + 40,
.hsync_end = 800 + 40 + 18,
.htotal = 800 + 40 + 18 + 20,

.vdisplay = 1280,
.vsync_start = 1280 + 20,
.vsync_end = 1280 + 20 + 4,
.vtotal = 1280 + 20 + 4 + 20,

.width_mm = 127,
.height_mm = 199,
.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
},
.lanes = 4,
.format = MIPI_DSI_FMT_RGB888,
.init_cmds = imx8mm_display_8hd_a_init_cmds,
.num_init_cmds = ARRAY_SIZE(imx8mm_display_8hd_a_init_cmds),
};

static int jadard_dsi_probe(struct mipi_dsi_device *dsi)
{
struct device *dev = &dsi->dev;
const struct jadard_panel_desc *desc;
struct jadard *jadard;
int ret;

pr_info("jadard_dsi_probe entry --------> \n");
jadard = devm_kzalloc(&dsi->dev, sizeof(*jadard), GFP_KERNEL);
if (!jadard)
return -ENOMEM;

desc = of_device_get_match_data(dev);
dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_NO_EOT_PACKET;
dsi->format = desc->format;
dsi->lanes = desc->lanes;

jadard->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(jadard->reset)) {
DRM_DEV_ERROR(&dsi->dev, "failed to get our reset GPIO\n");
return PTR_ERR(jadard->reset);
}

jadard->vdd = devm_regulator_get(dev, "vdd");
if (IS_ERR(jadard->vdd)) {
DRM_DEV_ERROR(&dsi->dev, "failed to get vdd regulator\n");
return PTR_ERR(jadard->vdd);
}

jadard->vccio = devm_regulator_get(dev, "vccio");
if (IS_ERR(jadard->vccio)) {
DRM_DEV_ERROR(&dsi->dev, "failed to get vccio regulator\n");
return PTR_ERR(jadard->vccio);
}

drm_panel_init(&jadard->panel, dev, &jadard_funcs,
DRM_MODE_CONNECTOR_DSI);

ret = drm_panel_of_backlight(&jadard->panel);
if (ret)
return ret;

drm_panel_add(&jadard->panel);

mipi_dsi_set_drvdata(dsi, jadard);
jadard->dsi = dsi;
jadard->desc = desc;

ret = mipi_dsi_attach(dsi);
if (ret < 0)
drm_panel_remove(&jadard->panel);

pr_info("jadard_dsi_probe exit --------> \n");
return ret;
}

static void jadard_dsi_remove(struct mipi_dsi_device *dsi)
{
struct jadard *jadard = mipi_dsi_get_drvdata(dsi);

mipi_dsi_detach(dsi);
drm_panel_remove(&jadard->panel);
}

static const struct of_device_id jadard_of_match[] = {
{
.compatible = "chongzhou,cz101b4001",
.data = &cz101b4001_desc
},
{
.compatible = "radxa,display-10hd-ad001",
.data = &cz101b4001_desc
},
{
.compatible = "radxa,display-8hd-ad002",
.data = &radxa_display_8hd_ad002_desc
},
{
.compatible = "jadard,jd9365da-h3",
.data = &imx8mm_display_8hd_a_desc
},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, jadard_of_match);

static struct mipi_dsi_driver jadard_driver = {
.probe = jadard_dsi_probe,
.remove = jadard_dsi_remove,
.driver = {
.name = "jadard-jd9365da",
.of_match_table = jadard_of_match,
},
};
module_mipi_dsi_driver(jadard_driver);

MODULE_AUTHOR("Jagan Teki <jagan@xxxxxxxxxx>");
MODULE_AUTHOR("Stephen Chen <stephen@xxxxxxxxx>");
MODULE_DESCRIPTION("Jadard JD9365DA-H3 WXGA DSI panel");
MODULE_LICENSE("GPL");

Attachment: imx8mm.dtsi
Description: Binary data

// SPDX-License-Identifier: GPL-2.0-only
/*
* Samsung MIPI DSIM bridge driver.
*
* Copyright (C) 2021 Amarula Solutions(India)
* Copyright (c) 2014 Samsung Electronics Co., Ltd
* Author: Jagan Teki <jagan@xxxxxxxxxxxxxxxxxxxx>
*
* Based on exynos_drm_dsi from
* Tomasz Figa <t.figa@xxxxxxxxxxx>
*/

#include <asm/unaligned.h>

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/media-bus-format.h>
#include <linux/of.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>

#include <video/mipi_display.h>

#include <drm/bridge/samsung-dsim.h>
#include <drm/drm_panel.h>
#include <drm/drm_print.h>

/* returns true iff both arguments logically differs */
#define NEQV(a, b) (!(a) ^ !(b))

/* DSIM_STATUS */
#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
#define DSIM_STOP_STATE_CLK BIT(8)
#define DSIM_TX_READY_HS_CLK BIT(10)
#define DSIM_PLL_STABLE BIT(31)

/* DSIM_SWRST */
#define DSIM_FUNCRST BIT(16)
#define DSIM_SWRST BIT(0)

/* DSIM_TIMEOUT */
#define DSIM_LPDR_TIMEOUT(x) ((x) << 0)
#define DSIM_BTA_TIMEOUT(x) ((x) << 16)

/* DSIM_CLKCTRL */
#define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0)
#define DSIM_ESC_PRESCALER_MASK (0xffff << 0)
#define DSIM_LANE_ESC_CLK_EN_CLK BIT(19)
#define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20)
#define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20)
#define DSIM_BYTE_CLKEN BIT(24)
#define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25)
#define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25)
#define DSIM_PLL_BYPASS BIT(27)
#define DSIM_ESC_CLKEN BIT(28)
#define DSIM_TX_REQUEST_HSCLK BIT(31)

/* DSIM_CONFIG */
#define DSIM_LANE_EN_CLK BIT(0)
#define DSIM_LANE_EN(x) (((x) & 0xf) << 1)
#define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5)
#define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8)
#define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12)
#define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12)
#define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12)
#define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12)
#define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12)
#define DSIM_SUB_VC (((x) & 0x3) << 16)
#define DSIM_MAIN_VC (((x) & 0x3) << 18)
#define DSIM_HSA_DISABLE_MODE BIT(20)
#define DSIM_HBP_DISABLE_MODE BIT(21)
#define DSIM_HFP_DISABLE_MODE BIT(22)
/*
* The i.MX 8M Mini Applications Processor Reference Manual,
* Rev. 3, 11/2020 Page 4091
* The i.MX 8M Nano Applications Processor Reference Manual,
* Rev. 2, 07/2022 Page 3058
* The i.MX 8M Plus Applications Processor Reference Manual,
* Rev. 1, 06/2021 Page 5436
* all claims this bit is 'HseDisableMode' with the definition
* 0 = Disables transfer
* 1 = Enables transfer
*
* This clearly states that HSE is not a disabled bit.
*
* The naming convention follows as per the manual and the
* driver logic is based on the MIPI_DSI_MODE_VIDEO_HSE flag.
*/
#define DSIM_HSE_DISABLE_MODE BIT(23)
#define DSIM_AUTO_MODE BIT(24)
#define DSIM_VIDEO_MODE BIT(25)
#define DSIM_BURST_MODE BIT(26)
#define DSIM_SYNC_INFORM BIT(27)
#define DSIM_EOT_DISABLE BIT(28)
#define DSIM_MFLUSH_VS BIT(29)
/* This flag is valid only for exynos3250/3472/5260/5430 */
#define DSIM_CLKLANE_STOP BIT(30)

/* DSIM_ESCMODE */
#define DSIM_TX_TRIGGER_RST BIT(4)
#define DSIM_TX_LPDT_LP BIT(6)
#define DSIM_CMD_LPDT_LP BIT(7)
#define DSIM_FORCE_BTA BIT(16)
#define DSIM_FORCE_STOP_STATE BIT(20)
#define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21)
#define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21)

/* DSIM_MDRESOL */
#define DSIM_MAIN_STAND_BY BIT(31)
#define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16)
#define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0)

/* DSIM_MVPORCH */
#define DSIM_CMD_ALLOW(x) ((x) << 28)
#define DSIM_STABLE_VFP(x) ((x) << 16)
#define DSIM_MAIN_VBP(x) ((x) << 0)
#define DSIM_CMD_ALLOW_MASK (0xf << 28)
#define DSIM_STABLE_VFP_MASK (0x7ff << 16)
#define DSIM_MAIN_VBP_MASK (0x7ff << 0)

/* DSIM_MHPORCH */
#define DSIM_MAIN_HFP(x) ((x) << 16)
#define DSIM_MAIN_HBP(x) ((x) << 0)
#define DSIM_MAIN_HFP_MASK ((0xffff) << 16)
#define DSIM_MAIN_HBP_MASK ((0xffff) << 0)

/* DSIM_MSYNC */
#define DSIM_MAIN_VSA(x) ((x) << 22)
#define DSIM_MAIN_HSA(x) ((x) << 0)
#define DSIM_MAIN_VSA_MASK ((0x3ff) << 22)
#define DSIM_MAIN_HSA_MASK ((0xffff) << 0)

/* DSIM_SDRESOL */
#define DSIM_SUB_STANDY(x) ((x) << 31)
#define DSIM_SUB_VRESOL(x) ((x) << 16)
#define DSIM_SUB_HRESOL(x) ((x) << 0)
#define DSIM_SUB_STANDY_MASK ((0x1) << 31)
#define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16)
#define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0)

/* DSIM_INTSRC */
#define DSIM_INT_PLL_STABLE BIT(31)
#define DSIM_INT_SW_RST_RELEASE BIT(30)
#define DSIM_INT_SFR_FIFO_EMPTY BIT(29)
#define DSIM_INT_SFR_HDR_FIFO_EMPTY BIT(28)
#define DSIM_INT_BTA BIT(25)
#define DSIM_INT_FRAME_DONE BIT(24)
#define DSIM_INT_RX_TIMEOUT BIT(21)
#define DSIM_INT_BTA_TIMEOUT BIT(20)
#define DSIM_INT_RX_DONE BIT(18)
#define DSIM_INT_RX_TE BIT(17)
#define DSIM_INT_RX_ACK BIT(16)
#define DSIM_INT_RX_ECC_ERR BIT(15)
#define DSIM_INT_RX_CRC_ERR BIT(14)

/* DSIM_FIFOCTRL */
#define DSIM_RX_DATA_FULL BIT(25)
#define DSIM_RX_DATA_EMPTY BIT(24)
#define DSIM_SFR_HEADER_FULL BIT(23)
#define DSIM_SFR_HEADER_EMPTY BIT(22)
#define DSIM_SFR_PAYLOAD_FULL BIT(21)
#define DSIM_SFR_PAYLOAD_EMPTY BIT(20)
#define DSIM_I80_HEADER_FULL BIT(19)
#define DSIM_I80_HEADER_EMPTY BIT(18)
#define DSIM_I80_PAYLOAD_FULL BIT(17)
#define DSIM_I80_PAYLOAD_EMPTY BIT(16)
#define DSIM_SD_HEADER_FULL BIT(15)
#define DSIM_SD_HEADER_EMPTY BIT(14)
#define DSIM_SD_PAYLOAD_FULL BIT(13)
#define DSIM_SD_PAYLOAD_EMPTY BIT(12)
#define DSIM_MD_HEADER_FULL BIT(11)
#define DSIM_MD_HEADER_EMPTY BIT(10)
#define DSIM_MD_PAYLOAD_FULL BIT(9)
#define DSIM_MD_PAYLOAD_EMPTY BIT(8)
#define DSIM_RX_FIFO BIT(4)
#define DSIM_SFR_FIFO BIT(3)
#define DSIM_I80_FIFO BIT(2)
#define DSIM_SD_FIFO BIT(1)
#define DSIM_MD_FIFO BIT(0)

/* DSIM_PHYACCHR */
#define DSIM_AFC_EN BIT(14)
#define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)

/* DSIM_PLLCTRL */
#define DSIM_PLL_DPDNSWAP_CLK (1 << 25)
#define DSIM_PLL_DPDNSWAP_DAT (1 << 24)
#define DSIM_FREQ_BAND(x) ((x) << 24)
#define DSIM_PLL_EN BIT(23)
#define DSIM_PLL_P(x, offset) ((x) << (offset))
#define DSIM_PLL_M(x) ((x) << 4)
#define DSIM_PLL_S(x) ((x) << 1)

/* DSIM_PHYCTRL */
#define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0)
#define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP BIT(30)
#define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP BIT(14)

/* DSIM_PHYTIMING */
#define DSIM_PHYTIMING_LPX(x) ((x) << 8)
#define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0)

/* DSIM_PHYTIMING1 */
#define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24)
#define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16)
#define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8)
#define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0)

/* DSIM_PHYTIMING2 */
#define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16)
#define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8)
#define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0)

#define DSI_MAX_BUS_WIDTH 4
#define DSI_NUM_VIRTUAL_CHANNELS 4
#define DSI_TX_FIFO_SIZE 2048
#define DSI_RX_FIFO_SIZE 256
#define DSI_XFER_TIMEOUT_MS 100
#define DSI_RX_FIFO_EMPTY 0x30800002

#define OLD_SCLK_MIPI_CLK_NAME "pll_clk"

#define PS_TO_CYCLE(ps, hz) DIV64_U64_ROUND_CLOSEST(((ps) * (hz)), 1000000000000ULL)

static const char *const clk_names[5] = {
"bus_clk",
"sclk_mipi",
"phyclk_mipidphy0_bitclkdiv8",
"phyclk_mipidphy0_rxclkesc0",
"sclk_rgb_vclk_to_dsim0"
};

enum samsung_dsim_transfer_type {
EXYNOS_DSI_TX,
EXYNOS_DSI_RX,
};

enum reg_idx {
DSIM_STATUS_REG, /* Status register */
DSIM_SWRST_REG, /* Software reset register */
DSIM_CLKCTRL_REG, /* Clock control register */
DSIM_TIMEOUT_REG, /* Time out register */
DSIM_CONFIG_REG, /* Configuration register */
DSIM_ESCMODE_REG, /* Escape mode register */
DSIM_MDRESOL_REG,
DSIM_MVPORCH_REG, /* Main display Vporch register */
DSIM_MHPORCH_REG, /* Main display Hporch register */
DSIM_MSYNC_REG, /* Main display sync area register */
DSIM_INTSRC_REG, /* Interrupt source register */
DSIM_INTMSK_REG, /* Interrupt mask register */
DSIM_PKTHDR_REG, /* Packet Header FIFO register */
DSIM_PAYLOAD_REG, /* Payload FIFO register */
DSIM_RXFIFO_REG, /* Read FIFO register */
DSIM_FIFOCTRL_REG, /* FIFO status and control register */
DSIM_PLLCTRL_REG, /* PLL control register */
DSIM_PHYCTRL_REG,
DSIM_PHYTIMING_REG,
DSIM_PHYTIMING1_REG,
DSIM_PHYTIMING2_REG,
NUM_REGS
};

static const unsigned int exynos_reg_ofs[] = {
[DSIM_STATUS_REG] = 0x00,
[DSIM_SWRST_REG] = 0x04,
[DSIM_CLKCTRL_REG] = 0x08,
[DSIM_TIMEOUT_REG] = 0x0c,
[DSIM_CONFIG_REG] = 0x10,
[DSIM_ESCMODE_REG] = 0x14,
[DSIM_MDRESOL_REG] = 0x18,
[DSIM_MVPORCH_REG] = 0x1c,
[DSIM_MHPORCH_REG] = 0x20,
[DSIM_MSYNC_REG] = 0x24,
[DSIM_INTSRC_REG] = 0x2c,
[DSIM_INTMSK_REG] = 0x30,
[DSIM_PKTHDR_REG] = 0x34,
[DSIM_PAYLOAD_REG] = 0x38,
[DSIM_RXFIFO_REG] = 0x3c,
[DSIM_FIFOCTRL_REG] = 0x44,
[DSIM_PLLCTRL_REG] = 0x4c,
[DSIM_PHYCTRL_REG] = 0x5c,
[DSIM_PHYTIMING_REG] = 0x64,
[DSIM_PHYTIMING1_REG] = 0x68,
[DSIM_PHYTIMING2_REG] = 0x6c,
};

static const unsigned int exynos5433_reg_ofs[] = {
[DSIM_STATUS_REG] = 0x04,
[DSIM_SWRST_REG] = 0x0C,
[DSIM_CLKCTRL_REG] = 0x10,
[DSIM_TIMEOUT_REG] = 0x14,
[DSIM_CONFIG_REG] = 0x18,
[DSIM_ESCMODE_REG] = 0x1C,
[DSIM_MDRESOL_REG] = 0x20,
[DSIM_MVPORCH_REG] = 0x24,
[DSIM_MHPORCH_REG] = 0x28,
[DSIM_MSYNC_REG] = 0x2C,
[DSIM_INTSRC_REG] = 0x34,
[DSIM_INTMSK_REG] = 0x38,
[DSIM_PKTHDR_REG] = 0x3C,
[DSIM_PAYLOAD_REG] = 0x40,
[DSIM_RXFIFO_REG] = 0x44,
[DSIM_FIFOCTRL_REG] = 0x4C,
[DSIM_PLLCTRL_REG] = 0x94,
[DSIM_PHYCTRL_REG] = 0xA4,
[DSIM_PHYTIMING_REG] = 0xB4,
[DSIM_PHYTIMING1_REG] = 0xB8,
[DSIM_PHYTIMING2_REG] = 0xBC,
};

enum reg_value_idx {
RESET_TYPE,
PLL_TIMER,
STOP_STATE_CNT,
PHYCTRL_ULPS_EXIT,
PHYCTRL_VREG_LP,
PHYCTRL_SLEW_UP,
PHYTIMING_LPX,
PHYTIMING_HS_EXIT,
PHYTIMING_CLK_PREPARE,
PHYTIMING_CLK_ZERO,
PHYTIMING_CLK_POST,
PHYTIMING_CLK_TRAIL,
PHYTIMING_HS_PREPARE,
PHYTIMING_HS_ZERO,
PHYTIMING_HS_TRAIL
};

static const unsigned int reg_values[] = {
[RESET_TYPE] = DSIM_SWRST,
[PLL_TIMER] = 500,
[STOP_STATE_CNT] = 0xf,
[PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af),
[PHYCTRL_VREG_LP] = 0,
[PHYCTRL_SLEW_UP] = 0,
[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27),
[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09),
[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
};

static const unsigned int exynos5422_reg_values[] = {
[RESET_TYPE] = DSIM_SWRST,
[PLL_TIMER] = 500,
[STOP_STATE_CNT] = 0xf,
[PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf),
[PHYCTRL_VREG_LP] = 0,
[PHYCTRL_SLEW_UP] = 0,
[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08),
[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d),
[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30),
[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a),
[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c),
[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11),
[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d),
};

static const unsigned int exynos5433_reg_values[] = {
[RESET_TYPE] = DSIM_FUNCRST,
[PLL_TIMER] = 22200,
[STOP_STATE_CNT] = 0xa,
[PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190),
[PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP,
[PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP,
[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07),
[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c),
[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d),
[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09),
[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b),
[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10),
[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
};

static const unsigned int imx8mm_dsim_reg_values[] = {
[RESET_TYPE] = DSIM_SWRST,
[PLL_TIMER] = 500,
[STOP_STATE_CNT] = 0xf,
[PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf),
[PHYCTRL_VREG_LP] = 0,
[PHYCTRL_SLEW_UP] = 0,
[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x26),
[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x08),
[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
};

static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = {
.reg_ofs = exynos_reg_ofs,
.plltmr_reg = 0x50,
.has_freqband = 1,
.has_clklane_stop = 1,
.num_clks = 2,
.max_freq = 1000,
.wait_for_reset = 1,
.num_bits_resol = 11,
.pll_p_offset = 13,
.reg_values = reg_values,
.m_min = 41,
.m_max = 125,
.min_freq = 500,
.has_broken_fifoctrl_emptyhdr = 1,
};

static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = {
.reg_ofs = exynos_reg_ofs,
.plltmr_reg = 0x50,
.has_freqband = 1,
.has_clklane_stop = 1,
.num_clks = 2,
.max_freq = 1000,
.wait_for_reset = 1,
.num_bits_resol = 11,
.pll_p_offset = 13,
.reg_values = reg_values,
.m_min = 41,
.m_max = 125,
.min_freq = 500,
.has_broken_fifoctrl_emptyhdr = 1,
};

static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = {
.reg_ofs = exynos_reg_ofs,
.plltmr_reg = 0x58,
.num_clks = 2,
.max_freq = 1000,
.wait_for_reset = 1,
.num_bits_resol = 11,
.pll_p_offset = 13,
.reg_values = reg_values,
.m_min = 41,
.m_max = 125,
.min_freq = 500,
};

static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = {
.reg_ofs = exynos5433_reg_ofs,
.plltmr_reg = 0xa0,
.has_clklane_stop = 1,
.num_clks = 5,
.max_freq = 1500,
.wait_for_reset = 0,
.num_bits_resol = 12,
.pll_p_offset = 13,
.reg_values = exynos5433_reg_values,
.m_min = 41,
.m_max = 125,
.min_freq = 500,
};

static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = {
.reg_ofs = exynos5433_reg_ofs,
.plltmr_reg = 0xa0,
.has_clklane_stop = 1,
.num_clks = 2,
.max_freq = 1500,
.wait_for_reset = 1,
.num_bits_resol = 12,
.pll_p_offset = 13,
.reg_values = exynos5422_reg_values,
.m_min = 41,
.m_max = 125,
.min_freq = 500,
};

static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = {
.reg_ofs = exynos5433_reg_ofs,
.plltmr_reg = 0xa0,
.has_clklane_stop = 1,
.num_clks = 2,
.max_freq = 2100,
.wait_for_reset = 0,
.num_bits_resol = 12,
/*
* Unlike Exynos, PLL_P(PMS_P) offset 14 is used in i.MX8M Mini/Nano/Plus
* downstream driver - drivers/gpu/drm/bridge/sec-dsim.c
*/
.pll_p_offset = 14,
.reg_values = imx8mm_dsim_reg_values,
.m_min = 64,
.m_max = 1023,
.min_freq = 1050,
};

static const struct samsung_dsim_driver_data *
samsung_dsim_types[DSIM_TYPE_COUNT] = {
[DSIM_TYPE_EXYNOS3250] = &exynos3_dsi_driver_data,
[DSIM_TYPE_EXYNOS4210] = &exynos4_dsi_driver_data,
[DSIM_TYPE_EXYNOS5410] = &exynos5_dsi_driver_data,
[DSIM_TYPE_EXYNOS5422] = &exynos5422_dsi_driver_data,
[DSIM_TYPE_EXYNOS5433] = &exynos5433_dsi_driver_data,
[DSIM_TYPE_IMX8MM] = &imx8mm_dsi_driver_data,
[DSIM_TYPE_IMX8MP] = &imx8mm_dsi_driver_data,
};

static inline struct samsung_dsim *host_to_dsi(struct mipi_dsi_host *h)
{
return container_of(h, struct samsung_dsim, dsi_host);
}

static inline struct samsung_dsim *bridge_to_dsi(struct drm_bridge *b)
{
return container_of(b, struct samsung_dsim, bridge);
}

static inline void samsung_dsim_write(struct samsung_dsim *dsi,
enum reg_idx idx, u32 val)
{
writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
}

static inline u32 samsung_dsim_read(struct samsung_dsim *dsi, enum reg_idx idx)
{
return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
}

static void samsung_dsim_wait_for_reset(struct samsung_dsim *dsi)
{
if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
return;

dev_err(dsi->dev, "timeout waiting for reset\n");
}

static void samsung_dsim_reset(struct samsung_dsim *dsi)
{
u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE];

reinit_completion(&dsi->completed);
samsung_dsim_write(dsi, DSIM_SWRST_REG, reset_val);
}

#ifndef MHZ
#define MHZ (1000 * 1000)
#endif

static unsigned long samsung_dsim_pll_find_pms(struct samsung_dsim *dsi,
unsigned long fin,
unsigned long fout,
u8 *p, u16 *m, u8 *s)
{
const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
unsigned long best_freq = 0;
u32 min_delta = 0xffffffff;
u8 p_min, p_max;
u8 _p, best_p;
u16 _m, best_m;
u8 _s, best_s;

p_min = DIV_ROUND_UP(fin, (12 * MHZ));
p_max = fin / (6 * MHZ);

for (_p = p_min; _p <= p_max; ++_p) {
for (_s = 0; _s <= 5; ++_s) {
u64 tmp;
u32 delta;

tmp = (u64)fout * (_p << _s);
do_div(tmp, fin);
_m = tmp;
if (_m < driver_data->m_min || _m > driver_data->m_max)
continue;

tmp = (u64)_m * fin;
do_div(tmp, _p);
if (tmp < driver_data->min_freq * MHZ ||
tmp > driver_data->max_freq * MHZ)
continue;

tmp = (u64)_m * fin;
do_div(tmp, _p << _s);

delta = abs(fout - tmp);
if (delta < min_delta) {
best_p = _p;
best_m = _m;
best_s = _s;
min_delta = delta;
best_freq = tmp;
}
}
}

if (best_freq) {
*p = best_p;
*m = best_m;
*s = best_s;
}

return best_freq;
}

static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi,
unsigned long freq)
{
const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
unsigned long fin, fout;
int timeout;
u8 p, s;
u16 m;
u32 reg;

fin = dsi->pll_clk_rate;
fout = samsung_dsim_pll_find_pms(dsi, fin, freq, &p, &m, &s);
if (!fout) {
dev_err(dsi->dev,
"failed to find PLL PMS for requested frequency\n");
return 0;
}
dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);

writel(driver_data->reg_values[PLL_TIMER],
dsi->reg_base + driver_data->plltmr_reg);

reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) |
DSIM_PLL_M(m) | DSIM_PLL_S(s);

if (driver_data->has_freqband) {
static const unsigned long freq_bands[] = {
100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
770 * MHZ, 870 * MHZ, 950 * MHZ,
};
int band;

for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
if (fout < freq_bands[band])
break;

dev_dbg(dsi->dev, "band %d\n", band);

reg |= DSIM_FREQ_BAND(band);
}

if (dsi->swap_dn_dp_clk)
reg |= DSIM_PLL_DPDNSWAP_CLK;
if (dsi->swap_dn_dp_data)
reg |= DSIM_PLL_DPDNSWAP_DAT;

samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);

timeout = 1000;
do {
if (timeout-- == 0) {
dev_err(dsi->dev, "PLL failed to stabilize\n");
return 0;
}
reg = samsung_dsim_read(dsi, DSIM_STATUS_REG);
} while ((reg & DSIM_PLL_STABLE) == 0);

dsi->hs_clock = fout;

return fout;
}

static int samsung_dsim_enable_clock(struct samsung_dsim *dsi)
{
unsigned long hs_clk, byte_clk, esc_clk, pix_clk;
unsigned long esc_div;
u32 reg;
struct drm_display_mode *m = &dsi->mode;
int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);

/* m->clock is in KHz */
pix_clk = m->clock * 1000;

/* Use burst_clk_rate if available, otherwise use the pix_clk */
if (dsi->burst_clk_rate)
hs_clk = samsung_dsim_set_pll(dsi, dsi->burst_clk_rate);
else
hs_clk = samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, dsi->lanes));

if (!hs_clk) {
dev_err(dsi->dev, "failed to configure DSI PLL\n");
return -EFAULT;
}

byte_clk = hs_clk / 8;
esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
esc_clk = byte_clk / esc_div;

if (esc_clk > 20 * MHZ) {
++esc_div;
esc_clk = byte_clk / esc_div;
}

dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
hs_clk, byte_clk, esc_clk);

reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG);
reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
| DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
| DSIM_BYTE_CLK_SRC_MASK);
reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
| DSIM_ESC_PRESCALER(esc_div)
| DSIM_LANE_ESC_CLK_EN_CLK
| DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
| DSIM_BYTE_CLK_SRC(0)
| DSIM_TX_REQUEST_HSCLK;
samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg);

return 0;
}

static void samsung_dsim_set_phy_ctrl(struct samsung_dsim *dsi)
{
const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
const unsigned int *reg_values = driver_data->reg_values;
u32 reg;
struct phy_configure_opts_mipi_dphy cfg;
int clk_prepare, lpx, clk_zero, clk_post, clk_trail;
int hs_exit, hs_prepare, hs_zero, hs_trail;
unsigned long long byte_clock = dsi->hs_clock / 8;

if (driver_data->has_freqband)
return;

phy_mipi_dphy_get_default_config_for_hsclk(dsi->hs_clock,
dsi->lanes, &cfg);

/*
* TODO:
* The tech Applications Processor manuals for i.MX8M Mini, Nano,
* and Plus don't state what the definition of the PHYTIMING
* bits are beyond their address and bit position.
* After reviewing NXP's downstream code, it appears
* that the various PHYTIMING registers take the number
* of cycles and use various dividers on them. This
* calculation does not result in an exact match to the
* downstream code, but it is very close to the values
* generated by their lookup table, and it appears
* to sync at a variety of resolutions. If someone
* can get a more accurate mathematical equation needed
* for these registers, this should be updated.
*/

lpx = PS_TO_CYCLE(cfg.lpx, byte_clock);
hs_exit = PS_TO_CYCLE(cfg.hs_exit, byte_clock);
clk_prepare = PS_TO_CYCLE(cfg.clk_prepare, byte_clock);
clk_zero = PS_TO_CYCLE(cfg.clk_zero, byte_clock);
clk_post = PS_TO_CYCLE(cfg.clk_post, byte_clock);
clk_trail = PS_TO_CYCLE(cfg.clk_trail, byte_clock);
hs_prepare = PS_TO_CYCLE(cfg.hs_prepare, byte_clock);
hs_zero = PS_TO_CYCLE(cfg.hs_zero, byte_clock);
hs_trail = PS_TO_CYCLE(cfg.hs_trail, byte_clock);

/* B D-PHY: D-PHY Master & Slave Analog Block control */
reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] |
reg_values[PHYCTRL_SLEW_UP];

samsung_dsim_write(dsi, DSIM_PHYCTRL_REG, reg);

/*
* T LPX: Transmitted length of any Low-Power state period
* T HS-EXIT: Time that the transmitter drives LP-11 following a HS
* burst
*/

reg = DSIM_PHYTIMING_LPX(lpx) | DSIM_PHYTIMING_HS_EXIT(hs_exit);

samsung_dsim_write(dsi, DSIM_PHYTIMING_REG, reg);

/*
* T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
* Line state immediately before the HS-0 Line state starting the
* HS transmission
* T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to
* transmitting the Clock.
* T CLK_POST: Time that the transmitter continues to send HS clock
* after the last associated Data Lane has transitioned to LP Mode
* Interval is defined as the period from the end of T HS-TRAIL to
* the beginning of T CLK-TRAIL
* T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
* the last payload clock bit of a HS transmission burst
*/

reg = DSIM_PHYTIMING1_CLK_PREPARE(clk_prepare) |
DSIM_PHYTIMING1_CLK_ZERO(clk_zero) |
DSIM_PHYTIMING1_CLK_POST(clk_post) |
DSIM_PHYTIMING1_CLK_TRAIL(clk_trail);

samsung_dsim_write(dsi, DSIM_PHYTIMING1_REG, reg);

/*
* T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
* Line state immediately before the HS-0 Line state starting the
* HS transmission
* T HS-ZERO: Time that the transmitter drives the HS-0 state prior to
* transmitting the Sync sequence.
* T HS-TRAIL: Time that the transmitter drives the flipped differential
* state after last payload data bit of a HS transmission burst
*/

reg = DSIM_PHYTIMING2_HS_PREPARE(hs_prepare) |
DSIM_PHYTIMING2_HS_ZERO(hs_zero) |
DSIM_PHYTIMING2_HS_TRAIL(hs_trail);

samsung_dsim_write(dsi, DSIM_PHYTIMING2_REG, reg);
}

static void samsung_dsim_disable_clock(struct samsung_dsim *dsi)
{
u32 reg;

reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG);
reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
| DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg);

reg = samsung_dsim_read(dsi, DSIM_PLLCTRL_REG);
reg &= ~DSIM_PLL_EN;
samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
}

static void samsung_dsim_enable_lane(struct samsung_dsim *dsi, u32 lane)
{
u32 reg = samsung_dsim_read(dsi, DSIM_CONFIG_REG);

reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK |
DSIM_LANE_EN(lane));
samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg);
}

static int samsung_dsim_init_link(struct samsung_dsim *dsi)
{
const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
int timeout;
u32 reg;
u32 lanes_mask;

/* Initialize FIFO pointers */
reg = samsung_dsim_read(dsi, DSIM_FIFOCTRL_REG);
reg &= ~0x1f;
samsung_dsim_write(dsi, DSIM_FIFOCTRL_REG, reg);

usleep_range(9000, 11000);

reg |= 0x1f;
samsung_dsim_write(dsi, DSIM_FIFOCTRL_REG, reg);
usleep_range(9000, 11000);

/* DSI configuration */
reg = 0;

/*
* The first bit of mode_flags specifies display configuration.
* If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
* mode, otherwise it will support command mode.
*/
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
reg |= DSIM_VIDEO_MODE;

/*
* The user manual describes that following bits are ignored in
* command mode.
*/
if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
reg |= DSIM_MFLUSH_VS;
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
reg |= DSIM_SYNC_INFORM;
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
reg |= DSIM_BURST_MODE;
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
reg |= DSIM_AUTO_MODE;
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
reg |= DSIM_HSE_DISABLE_MODE;
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP)
reg |= DSIM_HFP_DISABLE_MODE;
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP)
reg |= DSIM_HBP_DISABLE_MODE;
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA)
reg |= DSIM_HSA_DISABLE_MODE;
}

if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
reg |= DSIM_EOT_DISABLE;

switch (dsi->format) {
case MIPI_DSI_FMT_RGB888:
reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
break;
case MIPI_DSI_FMT_RGB666:
reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
break;
case MIPI_DSI_FMT_RGB666_PACKED:
reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
break;
case MIPI_DSI_FMT_RGB565:
reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
break;
default:
dev_err(dsi->dev, "invalid pixel format\n");
return -EINVAL;
}

/*
* Use non-continuous clock mode if the periparal wants and
* host controller supports
*
* In non-continous clock mode, host controller will turn off
* the HS clock between high-speed transmissions to reduce
* power consumption.
*/
if (driver_data->has_clklane_stop &&
dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
reg |= DSIM_CLKLANE_STOP;
samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg);

lanes_mask = BIT(dsi->lanes) - 1;
samsung_dsim_enable_lane(dsi, lanes_mask);

/* Check clock and data lane state are stop state */
timeout = 100;
do {
if (timeout-- == 0) {
dev_err(dsi->dev, "waiting for bus lanes timed out\n");
return -EFAULT;
}

reg = samsung_dsim_read(dsi, DSIM_STATUS_REG);
if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
!= DSIM_STOP_STATE_DAT(lanes_mask))
continue;
} while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));

reg = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
reg &= ~DSIM_STOP_STATE_CNT_MASK;
reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]);
samsung_dsim_write(dsi, DSIM_ESCMODE_REG, reg);

reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
samsung_dsim_write(dsi, DSIM_TIMEOUT_REG, reg);

return 0;
}

static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi)
{
struct drm_display_mode *m = &dsi->mode;
unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;
u32 reg;

if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
int byte_clk_khz = dsi->hs_clock / 1000 / 8;
int hfp = (m->hsync_start - m->hdisplay) * byte_clk_khz / m->clock;
int hbp = (m->htotal - m->hsync_end) * byte_clk_khz / m->clock;
int hsa = (m->hsync_end - m->hsync_start) * byte_clk_khz / m->clock;

/* remove packet overhead when possible */
hfp = max(hfp - 6, 0);
hbp = max(hbp - 6, 0);
hsa = max(hsa - 6, 0);

dev_dbg(dsi->dev, "calculated hfp: %u, hbp: %u, hsa: %u",
hfp, hbp, hsa);

reg = DSIM_CMD_ALLOW(0xf)
| DSIM_STABLE_VFP(m->vsync_start - m->vdisplay)
| DSIM_MAIN_VBP(m->vtotal - m->vsync_end);
samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg);

reg = DSIM_MAIN_HFP(hfp) | DSIM_MAIN_HBP(hbp);
samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg);

reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start)
| DSIM_MAIN_HSA(hsa);
samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg);
}
reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) |
DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol);

samsung_dsim_write(dsi, DSIM_MDRESOL_REG, reg);

dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay);
}

static void samsung_dsim_set_display_enable(struct samsung_dsim *dsi, bool enable)
{
u32 reg;

reg = samsung_dsim_read(dsi, DSIM_MDRESOL_REG);
if (enable)
reg |= DSIM_MAIN_STAND_BY;
else
reg &= ~DSIM_MAIN_STAND_BY;
samsung_dsim_write(dsi, DSIM_MDRESOL_REG, reg);
}

static int samsung_dsim_wait_for_hdr_fifo(struct samsung_dsim *dsi)
{
int timeout = 2000;

do {
u32 reg = samsung_dsim_read(dsi, DSIM_FIFOCTRL_REG);

if (!dsi->driver_data->has_broken_fifoctrl_emptyhdr) {
if (reg & DSIM_SFR_HEADER_EMPTY)
return 0;
} else {
if (!(reg & DSIM_SFR_HEADER_FULL)) {
/*
* Wait a little bit, so the pending data can
* actually leave the FIFO to avoid overflow.
*/
if (!cond_resched())
usleep_range(950, 1050);
return 0;
}
}

if (!cond_resched())
usleep_range(950, 1050);
} while (--timeout);

return -ETIMEDOUT;
}

static void samsung_dsim_set_cmd_lpm(struct samsung_dsim *dsi, bool lpm)
{
u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);

if (lpm)
v |= DSIM_CMD_LPDT_LP;
else
v &= ~DSIM_CMD_LPDT_LP;

samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v);
}

static void samsung_dsim_force_bta(struct samsung_dsim *dsi)
{
u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);

v |= DSIM_FORCE_BTA;
samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v);
}

static void samsung_dsim_send_to_fifo(struct samsung_dsim *dsi,
struct samsung_dsim_transfer *xfer)
{
struct device *dev = dsi->dev;
struct mipi_dsi_packet *pkt = &xfer->packet;
const u8 *payload = pkt->payload + xfer->tx_done;
u16 length = pkt->payload_length - xfer->tx_done;
bool first = !xfer->tx_done;
u32 reg;

dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n",
xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done);

if (length > DSI_TX_FIFO_SIZE)
length = DSI_TX_FIFO_SIZE;

xfer->tx_done += length;

/* Send payload */
while (length >= 4) {
reg = get_unaligned_le32(payload);
samsung_dsim_write(dsi, DSIM_PAYLOAD_REG, reg);
payload += 4;
length -= 4;
}

reg = 0;
switch (length) {
case 3:
reg |= payload[2] << 16;
fallthrough;
case 2:
reg |= payload[1] << 8;
fallthrough;
case 1:
reg |= payload[0];
samsung_dsim_write(dsi, DSIM_PAYLOAD_REG, reg);
break;
}

/* Send packet header */
if (!first)
return;

reg = get_unaligned_le32(pkt->header);
if (samsung_dsim_wait_for_hdr_fifo(dsi)) {
dev_err(dev, "waiting for header FIFO timed out\n");
return;
}

if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
dsi->state & DSIM_STATE_CMD_LPM)) {
samsung_dsim_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
dsi->state ^= DSIM_STATE_CMD_LPM;
}

samsung_dsim_write(dsi, DSIM_PKTHDR_REG, reg);

if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
samsung_dsim_force_bta(dsi);
}

static void samsung_dsim_read_from_fifo(struct samsung_dsim *dsi,
struct samsung_dsim_transfer *xfer)
{
u8 *payload = xfer->rx_payload + xfer->rx_done;
bool first = !xfer->rx_done;
struct device *dev = dsi->dev;
u16 length;
u32 reg;

if (first) {
reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);

switch (reg & 0x3f) {
case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
if (xfer->rx_len >= 2) {
payload[1] = reg >> 16;
++xfer->rx_done;
}
fallthrough;
case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
payload[0] = reg >> 8;
++xfer->rx_done;
xfer->rx_len = xfer->rx_done;
xfer->result = 0;
goto clear_fifo;
case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
dev_err(dev, "DSI Error Report: 0x%04x\n", (reg >> 8) & 0xffff);
xfer->result = 0;
goto clear_fifo;
}

length = (reg >> 8) & 0xffff;
if (length > xfer->rx_len) {
dev_err(dev,
"response too long (%u > %u bytes), stripping\n",
xfer->rx_len, length);
length = xfer->rx_len;
} else if (length < xfer->rx_len) {
xfer->rx_len = length;
}
}

length = xfer->rx_len - xfer->rx_done;
xfer->rx_done += length;

/* Receive payload */
while (length >= 4) {
reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
payload[0] = (reg >> 0) & 0xff;
payload[1] = (reg >> 8) & 0xff;
payload[2] = (reg >> 16) & 0xff;
payload[3] = (reg >> 24) & 0xff;
payload += 4;
length -= 4;
}

if (length) {
reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
switch (length) {
case 3:
payload[2] = (reg >> 16) & 0xff;
fallthrough;
case 2:
payload[1] = (reg >> 8) & 0xff;
fallthrough;
case 1:
payload[0] = reg & 0xff;
}
}

if (xfer->rx_done == xfer->rx_len)
xfer->result = 0;

clear_fifo:
length = DSI_RX_FIFO_SIZE / 4;
do {
reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
if (reg == DSI_RX_FIFO_EMPTY)
break;
} while (--length);
}

static void samsung_dsim_transfer_start(struct samsung_dsim *dsi)
{
unsigned long flags;
struct samsung_dsim_transfer *xfer;
bool start = false;

again:
spin_lock_irqsave(&dsi->transfer_lock, flags);

if (list_empty(&dsi->transfer_list)) {
spin_unlock_irqrestore(&dsi->transfer_lock, flags);
return;
}

xfer = list_first_entry(&dsi->transfer_list,
struct samsung_dsim_transfer, list);

spin_unlock_irqrestore(&dsi->transfer_lock, flags);

if (xfer->packet.payload_length &&
xfer->tx_done == xfer->packet.payload_length)
/* waiting for RX */
return;

samsung_dsim_send_to_fifo(dsi, xfer);

if (xfer->packet.payload_length || xfer->rx_len)
return;

xfer->result = 0;
complete(&xfer->completed);

spin_lock_irqsave(&dsi->transfer_lock, flags);

list_del_init(&xfer->list);
start = !list_empty(&dsi->transfer_list);

spin_unlock_irqrestore(&dsi->transfer_lock, flags);

if (start)
goto again;
}

static bool samsung_dsim_transfer_finish(struct samsung_dsim *dsi)
{
struct samsung_dsim_transfer *xfer;
unsigned long flags;
bool start = true;

spin_lock_irqsave(&dsi->transfer_lock, flags);

if (list_empty(&dsi->transfer_list)) {
spin_unlock_irqrestore(&dsi->transfer_lock, flags);
return false;
}

xfer = list_first_entry(&dsi->transfer_list,
struct samsung_dsim_transfer, list);

spin_unlock_irqrestore(&dsi->transfer_lock, flags);

dev_dbg(dsi->dev,
"> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n",
xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len,
xfer->rx_done);

if (xfer->tx_done != xfer->packet.payload_length)
return true;

if (xfer->rx_done != xfer->rx_len)
samsung_dsim_read_from_fifo(dsi, xfer);

if (xfer->rx_done != xfer->rx_len)
return true;

spin_lock_irqsave(&dsi->transfer_lock, flags);

list_del_init(&xfer->list);
start = !list_empty(&dsi->transfer_list);

spin_unlock_irqrestore(&dsi->transfer_lock, flags);

if (!xfer->rx_len)
xfer->result = 0;
complete(&xfer->completed);

return start;
}

static void samsung_dsim_remove_transfer(struct samsung_dsim *dsi,
struct samsung_dsim_transfer *xfer)
{
unsigned long flags;
bool start;

spin_lock_irqsave(&dsi->transfer_lock, flags);

if (!list_empty(&dsi->transfer_list) &&
xfer == list_first_entry(&dsi->transfer_list,
struct samsung_dsim_transfer, list)) {
list_del_init(&xfer->list);
start = !list_empty(&dsi->transfer_list);
spin_unlock_irqrestore(&dsi->transfer_lock, flags);
if (start)
samsung_dsim_transfer_start(dsi);
return;
}

list_del_init(&xfer->list);

spin_unlock_irqrestore(&dsi->transfer_lock, flags);
}

static int samsung_dsim_transfer(struct samsung_dsim *dsi,
struct samsung_dsim_transfer *xfer)
{
unsigned long flags;
bool stopped;

xfer->tx_done = 0;
xfer->rx_done = 0;
xfer->result = -ETIMEDOUT;
init_completion(&xfer->completed);

spin_lock_irqsave(&dsi->transfer_lock, flags);

stopped = list_empty(&dsi->transfer_list);
list_add_tail(&xfer->list, &dsi->transfer_list);

spin_unlock_irqrestore(&dsi->transfer_lock, flags);

if (stopped)
samsung_dsim_transfer_start(dsi);

wait_for_completion_timeout(&xfer->completed,
msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
if (xfer->result == -ETIMEDOUT) {
struct mipi_dsi_packet *pkt = &xfer->packet;

samsung_dsim_remove_transfer(dsi, xfer);
dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header,
(int)pkt->payload_length, pkt->payload);
return -ETIMEDOUT;
}

/* Also covers hardware timeout condition */
return xfer->result;
}

static irqreturn_t samsung_dsim_irq(int irq, void *dev_id)
{
struct samsung_dsim *dsi = dev_id;
u32 status;

status = samsung_dsim_read(dsi, DSIM_INTSRC_REG);
if (!status) {
static unsigned long j;

if (printk_timed_ratelimit(&j, 500))
dev_warn(dsi->dev, "spurious interrupt\n");
return IRQ_HANDLED;
}
samsung_dsim_write(dsi, DSIM_INTSRC_REG, status);

if (status & DSIM_INT_SW_RST_RELEASE) {
unsigned long mask = ~(DSIM_INT_RX_DONE |
DSIM_INT_SFR_FIFO_EMPTY |
DSIM_INT_SFR_HDR_FIFO_EMPTY |
DSIM_INT_RX_ECC_ERR |
DSIM_INT_SW_RST_RELEASE);
samsung_dsim_write(dsi, DSIM_INTMSK_REG, mask);
complete(&dsi->completed);
return IRQ_HANDLED;
}

if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
DSIM_INT_PLL_STABLE)))
return IRQ_HANDLED;

if (samsung_dsim_transfer_finish(dsi))
samsung_dsim_transfer_start(dsi);

return IRQ_HANDLED;
}

static void samsung_dsim_enable_irq(struct samsung_dsim *dsi)
{
enable_irq(dsi->irq);

if (dsi->te_gpio)
enable_irq(gpiod_to_irq(dsi->te_gpio));
}

static void samsung_dsim_disable_irq(struct samsung_dsim *dsi)
{
if (dsi->te_gpio)
disable_irq(gpiod_to_irq(dsi->te_gpio));

disable_irq(dsi->irq);
}

static int samsung_dsim_init(struct samsung_dsim *dsi)
{
const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;

pr_info("samsung_dsim_init entry ------<> \n");
if (dsi->state & DSIM_STATE_INITIALIZED)
return 0;

samsung_dsim_reset(dsi);
samsung_dsim_enable_irq(dsi);

if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST)
samsung_dsim_enable_lane(dsi, BIT(dsi->lanes) - 1);

samsung_dsim_enable_clock(dsi);
if (driver_data->wait_for_reset)
samsung_dsim_wait_for_reset(dsi);
samsung_dsim_set_phy_ctrl(dsi);
samsung_dsim_init_link(dsi);

dsi->state |= DSIM_STATE_INITIALIZED;

pr_info("samsung_dsim_init exit ------<> \n");
return 0;
}

static void samsung_dsim_atomic_pre_enable(struct drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)
{
struct samsung_dsim *dsi = bridge_to_dsi(bridge);
int ret;

if (dsi->state & DSIM_STATE_ENABLED)
return;

ret = pm_runtime_resume_and_get(dsi->dev);
if (ret < 0) {
dev_err(dsi->dev, "failed to enable DSI device.\n");
return;
}

dsi->state |= DSIM_STATE_ENABLED;

/*
* For Exynos-DSIM the downstream bridge, or panel are expecting
* the host initialization during DSI transfer.
*/
if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) {
ret = samsung_dsim_init(dsi);
if (ret)
return;
}
}

static void samsung_dsim_atomic_enable(struct drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)
{
struct samsung_dsim *dsi = bridge_to_dsi(bridge);

samsung_dsim_set_display_mode(dsi);
samsung_dsim_set_display_enable(dsi, true);

dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE;
}

static void samsung_dsim_atomic_disable(struct drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)
{
struct samsung_dsim *dsi = bridge_to_dsi(bridge);

if (!(dsi->state & DSIM_STATE_ENABLED))
return;

dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE;
}

static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)
{
struct samsung_dsim *dsi = bridge_to_dsi(bridge);

samsung_dsim_set_display_enable(dsi, false);

dsi->state &= ~DSIM_STATE_ENABLED;
pm_runtime_put_sync(dsi->dev);
}

/*
* This pixel output formats list referenced from,
* AN13573 i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022
* 3.7.4 Pixel formats
* Table 14. DSI pixel packing formats
*/
static const u32 samsung_dsim_pixel_output_fmts[] = {
MEDIA_BUS_FMT_YUYV10_1X20,
MEDIA_BUS_FMT_YUYV12_1X24,
MEDIA_BUS_FMT_UYVY8_1X16,
MEDIA_BUS_FMT_RGB101010_1X30,
MEDIA_BUS_FMT_RGB121212_1X36,
MEDIA_BUS_FMT_RGB565_1X16,
MEDIA_BUS_FMT_RGB666_1X18,
MEDIA_BUS_FMT_RGB888_1X24,
};

static bool samsung_dsim_pixel_output_fmt_supported(u32 fmt)
{
int i;

if (fmt == MEDIA_BUS_FMT_FIXED)
return false;

for (i = 0; i < ARRAY_SIZE(samsung_dsim_pixel_output_fmts); i++) {
if (samsung_dsim_pixel_output_fmts[i] == fmt)
return true;
}

return false;
}

static u32 *
samsung_dsim_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
struct drm_bridge_state *bridge_state,
struct drm_crtc_state *crtc_state,
struct drm_connector_state *conn_state,
u32 output_fmt,
unsigned int *num_input_fmts)
{
u32 *input_fmts;

input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
if (!input_fmts)
return NULL;

if (!samsung_dsim_pixel_output_fmt_supported(output_fmt))
/*
* Some bridge/display drivers are still not able to pass the
* correct format, so handle those pipelines by falling back
* to the default format till the supported formats finalized.
*/
output_fmt = MEDIA_BUS_FMT_RGB888_1X24;

input_fmts[0] = output_fmt;
*num_input_fmts = 1;

return input_fmts;
}

static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
struct drm_bridge_state *bridge_state,
struct drm_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
{
struct samsung_dsim *dsi = bridge_to_dsi(bridge);
struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;

/*
* The i.MX8M Mini/Nano glue logic between LCDIF and DSIM
* inverts HS/VS/DE sync signals polarity, therefore, while
* i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020
* 13.6.3.5.2 RGB interface
* i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022
* 13.6.2.7.2 RGB interface
* both claim "Vsync, Hsync, and VDEN are active high signals.", the
* LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW.
*
* The i.MX8M Plus glue logic between LCDIFv3 and DSIM does not
* implement the same behavior, therefore LCDIFv3 must generate
* HS/VS/DE signals active HIGH.
*/
if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) {
adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
} else if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MP) {
adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
}

return 0;
}

static void samsung_dsim_mode_set(struct drm_bridge *bridge,
const struct drm_display_mode *mode,
const struct drm_display_mode *adjusted_mode)
{
struct samsung_dsim *dsi = bridge_to_dsi(bridge);

drm_mode_copy(&dsi->mode, adjusted_mode);
}

static int samsung_dsim_attach(struct drm_bridge *bridge,
enum drm_bridge_attach_flags flags)
{
struct samsung_dsim *dsi = bridge_to_dsi(bridge);

pr_info("samsung_dsim_attach entry ----> caller is %pS\n", __builtin_return_address(0));
return drm_bridge_attach(bridge->encoder, dsi->out_bridge, bridge,
flags);
}

static const struct drm_bridge_funcs samsung_dsim_bridge_funcs = {
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
.atomic_reset = drm_atomic_helper_bridge_reset,
.atomic_get_input_bus_fmts = samsung_dsim_atomic_get_input_bus_fmts,
.atomic_check = samsung_dsim_atomic_check,
.atomic_pre_enable = samsung_dsim_atomic_pre_enable,
.atomic_enable = samsung_dsim_atomic_enable,
.atomic_disable = samsung_dsim_atomic_disable,
.atomic_post_disable = samsung_dsim_atomic_post_disable,
.mode_set = samsung_dsim_mode_set,
.attach = samsung_dsim_attach,
};

static irqreturn_t samsung_dsim_te_irq_handler(int irq, void *dev_id)
{
struct samsung_dsim *dsi = (struct samsung_dsim *)dev_id;
const struct samsung_dsim_plat_data *pdata = dsi->plat_data;

if (pdata->host_ops && pdata->host_ops->te_irq_handler)
return pdata->host_ops->te_irq_handler(dsi);

return IRQ_HANDLED;
}

static int samsung_dsim_register_te_irq(struct samsung_dsim *dsi, struct device *dev)
{
int te_gpio_irq;
int ret;

dsi->te_gpio = devm_gpiod_get_optional(dev, "te", GPIOD_IN);
if (!dsi->te_gpio)
return 0;
else if (IS_ERR(dsi->te_gpio))
return dev_err_probe(dev, PTR_ERR(dsi->te_gpio), "failed to get te GPIO\n");

te_gpio_irq = gpiod_to_irq(dsi->te_gpio);

ret = request_threaded_irq(te_gpio_irq, samsung_dsim_te_irq_handler, NULL,
IRQF_TRIGGER_RISING | IRQF_NO_AUTOEN, "TE", dsi);
if (ret) {
dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
gpiod_put(dsi->te_gpio);
return ret;
}

return 0;
}

static int samsung_dsim_host_attach(struct mipi_dsi_host *host,
struct mipi_dsi_device *device)
{
struct samsung_dsim *dsi = host_to_dsi(host);
const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
struct device *dev = dsi->dev;
struct device_node *np = dev->of_node;
struct device_node *remote;
struct drm_panel *panel;
int ret;

pr_info("samsung_dsim_host_attach entry ---------<> \n");
/*
* Devices can also be child nodes when we also control that device
* through the upstream device (ie, MIPI-DCS for a MIPI-DSI device).
*
* Lookup for a child node of the given parent that isn't either port
* or ports.
*/
for_each_available_child_of_node(np, remote) {
if (of_node_name_eq(remote, "port") ||
of_node_name_eq(remote, "ports"))
continue;

goto of_find_panel_or_bridge;
}

/*
* of_graph_get_remote_node() produces a noisy error message if port
* node isn't found and the absence of the port is a legit case here,
* so at first we silently check whether graph presents in the
* device-tree node.
*/
if (!of_graph_is_present(np))
return -ENODEV;

remote = of_graph_get_remote_node(np, 1, 0);

of_find_panel_or_bridge:
if (!remote)
return -ENODEV;

panel = of_drm_find_panel(remote);
if (!IS_ERR(panel)) {
dsi->out_bridge = devm_drm_panel_bridge_add(dev, panel);
} else {
dsi->out_bridge = of_drm_find_bridge(remote);
if (!dsi->out_bridge)
dsi->out_bridge = ERR_PTR(-EINVAL);
}

of_node_put(remote);

if (IS_ERR(dsi->out_bridge)) {
ret = PTR_ERR(dsi->out_bridge);
DRM_DEV_ERROR(dev, "failed to find the bridge: %d\n", ret);
return ret;
}

DRM_DEV_INFO(dev, "Attached %s device\n", device->name);

drm_bridge_add(&dsi->bridge);

/*
* This is a temporary solution and should be made by more generic way.
*
* If attached panel device is for command mode one, dsi should register
* TE interrupt handler.
*/
if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) {
ret = samsung_dsim_register_te_irq(dsi, &device->dev);
if (ret)
return ret;
}

if (pdata->host_ops && pdata->host_ops->attach) {
pr_info("samsung_dsim_host_attach trigger samsung_dsim_host_ops attach ----< \n");
ret = pdata->host_ops->attach(dsi, device);
if (ret)
return ret;
}

pr_info("samsung_dsim_host_attach: before filling dsi->lanes, format info ===> \n");
dsi->lanes = device->lanes;
dsi->format = device->format;
dsi->mode_flags = device->mode_flags;

pr_info("samsung_dsim_host_attach exit --------> \n ");
return 0;
}

static void samsung_dsim_unregister_te_irq(struct samsung_dsim *dsi)
{
if (dsi->te_gpio) {
free_irq(gpiod_to_irq(dsi->te_gpio), dsi);
gpiod_put(dsi->te_gpio);
}
}

static int samsung_dsim_host_detach(struct mipi_dsi_host *host,
struct mipi_dsi_device *device)
{
struct samsung_dsim *dsi = host_to_dsi(host);
const struct samsung_dsim_plat_data *pdata = dsi->plat_data;

dsi->out_bridge = NULL;

if (pdata->host_ops && pdata->host_ops->detach)
pdata->host_ops->detach(dsi, device);

samsung_dsim_unregister_te_irq(dsi);

drm_bridge_remove(&dsi->bridge);

return 0;
}

static ssize_t samsung_dsim_host_transfer(struct mipi_dsi_host *host,
const struct mipi_dsi_msg *msg)
{
struct samsung_dsim *dsi = host_to_dsi(host);
struct samsung_dsim_transfer xfer;
int ret;

pr_info("samsung_dsim_host_transfer entry ====> \n");
if (!(dsi->state & DSIM_STATE_ENABLED))
return -EINVAL;

ret = samsung_dsim_init(dsi);
if (ret)
return ret;

ret = mipi_dsi_create_packet(&xfer.packet, msg);
if (ret < 0)
return ret;

xfer.rx_len = msg->rx_len;
xfer.rx_payload = msg->rx_buf;
xfer.flags = msg->flags;

ret = samsung_dsim_transfer(dsi, &xfer);
return (ret < 0) ? ret : xfer.rx_done;
}

static const struct mipi_dsi_host_ops samsung_dsim_ops = {
.attach = samsung_dsim_host_attach,
.detach = samsung_dsim_host_detach,
.transfer = samsung_dsim_host_transfer,
};

static int samsung_dsim_of_read_u32(const struct device_node *np,
const char *propname, u32 *out_value, bool optional)
{
int ret = of_property_read_u32(np, propname, out_value);

if (ret < 0 && !optional)
pr_err("%pOF: failed to get '%s' property\n", np, propname);

return ret;
}

static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
{
struct device *dev = dsi->dev;
struct device_node *node = dev->of_node;
u32 lane_polarities[5] = { 0 };
struct device_node *endpoint;
int i, nr_lanes, ret;
struct clk *pll_clk;

ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
&dsi->pll_clk_rate, 1);
/* If it doesn't exist, read it from the clock instead of failing */
if (ret < 0) {
dev_dbg(dev, "Using sclk_mipi for pll clock frequency\n");
pll_clk = devm_clk_get(dev, "sclk_mipi");
if (!IS_ERR(pll_clk))
dsi->pll_clk_rate = clk_get_rate(pll_clk);
else
return PTR_ERR(pll_clk);
}

/* If it doesn't exist, use pixel clock instead of failing */
ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency",
&dsi->burst_clk_rate, 1);
if (ret < 0) {
dev_dbg(dev, "Using pixel clock for HS clock frequency\n");
dsi->burst_clk_rate = 0;
}

ret = samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency",
&dsi->esc_clk_rate, 0);
if (ret < 0)
return ret;

endpoint = of_graph_get_endpoint_by_regs(node, 1, -1);
nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
if (nr_lanes > 0 && nr_lanes <= 4) {
/* Polarity 0 is clock lane, 1..4 are data lanes. */
of_property_read_u32_array(endpoint, "lane-polarities",
lane_polarities, nr_lanes + 1);
for (i = 1; i <= nr_lanes; i++) {
if (lane_polarities[1] != lane_polarities[i])
DRM_DEV_ERROR(dsi->dev, "Data lanes polarities do not match");
}
if (lane_polarities[0])
dsi->swap_dn_dp_clk = true;
if (lane_polarities[1])
dsi->swap_dn_dp_data = true;
}

return 0;
}

static int generic_dsim_register_host(struct samsung_dsim *dsi)
{
pr_info("generic_dsim_register_host entry ==========> \n");
return mipi_dsi_host_register(&dsi->dsi_host);
}

static void generic_dsim_unregister_host(struct samsung_dsim *dsi)
{
mipi_dsi_host_unregister(&dsi->dsi_host);
}

static const struct samsung_dsim_host_ops generic_dsim_host_ops = {
.register_host = generic_dsim_register_host,
.unregister_host = generic_dsim_unregister_host,
};

static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_high = {
.input_bus_flags = DRM_BUS_FLAG_DE_HIGH,
};

static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_low = {
.input_bus_flags = DRM_BUS_FLAG_DE_LOW,
};

int samsung_dsim_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct samsung_dsim *dsi;
int ret, i;

pr_info("samsung_dsim_probe entry --------------> \n");
dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
if (!dsi)
return -ENOMEM;

init_completion(&dsi->completed);
spin_lock_init(&dsi->transfer_lock);
INIT_LIST_HEAD(&dsi->transfer_list);

dsi->dsi_host.ops = &samsung_dsim_ops;
dsi->dsi_host.dev = dev;

dsi->dev = dev;
dsi->plat_data = of_device_get_match_data(dev);
dsi->driver_data = samsung_dsim_types[dsi->plat_data->hw_type];

dsi->supplies[0].supply = "vddcore";
dsi->supplies[1].supply = "vddio";
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
dsi->supplies);
if (ret)
return dev_err_probe(dev, ret, "failed to get regulators\n");

dsi->clks = devm_kcalloc(dev, dsi->driver_data->num_clks,
sizeof(*dsi->clks), GFP_KERNEL);
if (!dsi->clks)
return -ENOMEM;

for (i = 0; i < dsi->driver_data->num_clks; i++) {
dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
if (IS_ERR(dsi->clks[i])) {
if (strcmp(clk_names[i], "sclk_mipi") == 0) {
dsi->clks[i] = devm_clk_get(dev, OLD_SCLK_MIPI_CLK_NAME);
if (!IS_ERR(dsi->clks[i]))
continue;
}

dev_info(dev, "failed to get the clock: %s\n", clk_names[i]);
return PTR_ERR(dsi->clks[i]);
}
}

dsi->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(dsi->reg_base))
return PTR_ERR(dsi->reg_base);

dsi->phy = devm_phy_optional_get(dev, "dsim");
if (IS_ERR(dsi->phy)) {
dev_info(dev, "failed to get dsim phy\n");
return PTR_ERR(dsi->phy);
}

dsi->irq = platform_get_irq(pdev, 0);
if (dsi->irq < 0)
return dsi->irq;

ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
samsung_dsim_irq,
IRQF_ONESHOT | IRQF_NO_AUTOEN,
dev_name(dev), dsi);
if (ret) {
dev_err(dev, "failed to request dsi irq\n");
return ret;
}

ret = samsung_dsim_parse_dt(dsi);
if (ret)
return ret;

platform_set_drvdata(pdev, dsi);

pm_runtime_enable(dev);

dsi->bridge.funcs = &samsung_dsim_bridge_funcs;
dsi->bridge.of_node = dev->of_node;
dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;

/* DE_LOW: i.MX8M Mini/Nano LCDIF-DSIM glue logic inverts HS/VS/DE */
if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) {
dsi->bridge.timings = &samsung_dsim_bridge_timings_de_low;
pr_info("plat_data->hw_type is imx8mm core =========> \n");
}
else
dsi->bridge.timings = &samsung_dsim_bridge_timings_de_high;

if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->register_host)
ret = dsi->plat_data->host_ops->register_host(dsi);

if (ret)
goto err_disable_runtime;

pr_info("samsung_dsim_probe exit =========> \n");
return 0;

err_disable_runtime:
pm_runtime_disable(dev);

return ret;
}
EXPORT_SYMBOL_GPL(samsung_dsim_probe);

int samsung_dsim_remove(struct platform_device *pdev)
{
struct samsung_dsim *dsi = platform_get_drvdata(pdev);

pm_runtime_disable(&pdev->dev);

if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->unregister_host)
dsi->plat_data->host_ops->unregister_host(dsi);

return 0;
}
EXPORT_SYMBOL_GPL(samsung_dsim_remove);

static int __maybe_unused samsung_dsim_suspend(struct device *dev)
{
struct samsung_dsim *dsi = dev_get_drvdata(dev);
const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
int ret, i;

usleep_range(10000, 20000);

if (dsi->state & DSIM_STATE_INITIALIZED) {
dsi->state &= ~DSIM_STATE_INITIALIZED;

samsung_dsim_disable_clock(dsi);

samsung_dsim_disable_irq(dsi);
}

dsi->state &= ~DSIM_STATE_CMD_LPM;

phy_power_off(dsi->phy);

for (i = driver_data->num_clks - 1; i > -1; i--)
clk_disable_unprepare(dsi->clks[i]);

ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
if (ret < 0)
dev_err(dsi->dev, "cannot disable regulators %d\n", ret);

return 0;
}

static int __maybe_unused samsung_dsim_resume(struct device *dev)
{
struct samsung_dsim *dsi = dev_get_drvdata(dev);
const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
int ret, i;

ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
if (ret < 0) {
dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
return ret;
}

for (i = 0; i < driver_data->num_clks; i++) {
ret = clk_prepare_enable(dsi->clks[i]);
if (ret < 0)
goto err_clk;
}

ret = phy_power_on(dsi->phy);
if (ret < 0) {
dev_err(dsi->dev, "cannot enable phy %d\n", ret);
goto err_clk;
}

return 0;

err_clk:
while (--i > -1)
clk_disable_unprepare(dsi->clks[i]);
regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);

return ret;
}

const struct dev_pm_ops samsung_dsim_pm_ops = {
SET_RUNTIME_PM_OPS(samsung_dsim_suspend, samsung_dsim_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
EXPORT_SYMBOL_GPL(samsung_dsim_pm_ops);

static const struct samsung_dsim_plat_data samsung_dsim_imx8mm_pdata = {
.hw_type = DSIM_TYPE_IMX8MM,
.host_ops = &generic_dsim_host_ops,
};

static const struct samsung_dsim_plat_data samsung_dsim_imx8mp_pdata = {
.hw_type = DSIM_TYPE_IMX8MP,
.host_ops = &generic_dsim_host_ops,
};

static const struct of_device_id samsung_dsim_of_match[] = {
{
.compatible = "fsl,imx8mm-mipi-dsim",
.data = &samsung_dsim_imx8mm_pdata,
},
{
.compatible = "fsl,imx8mp-mipi-dsim",
.data = &samsung_dsim_imx8mp_pdata,
},
{ /* sentinel. */ }
};
MODULE_DEVICE_TABLE(of, samsung_dsim_of_match);

static struct platform_driver samsung_dsim_driver = {
.probe = samsung_dsim_probe,
.remove = samsung_dsim_remove,
.driver = {
.name = "samsung-dsim",
.pm = &samsung_dsim_pm_ops,
.of_match_table = samsung_dsim_of_match,
},
};

module_platform_driver(samsung_dsim_driver);

MODULE_AUTHOR("Jagan Teki <jagan@xxxxxxxxxxxxxxxxxxxx>");
MODULE_DESCRIPTION("Samsung MIPI DSIM controller bridge");
MODULE_LICENSE("GPL");