[PATCH] ASoC: ti: j721e-evm: Fix clock configuration for ti,j7200-cpb-audio compatible

[Jayesh Choudhary]

For 'ti,j7200-cpb-audio' compatible, there is support for only one PLL for
48k. For 11025, 22050, 44100 and 88200 sampling rates, due to absence of
J721E_CLK_PARENT_44100, we get EINVAL while running any audio application.
Add support for these rates by using the 48k parent clock and adjusting
the clock for these rates later in j721e_configure_refclk.

Fixes: 6748d0559059 ("ASoC: ti: Add custom machine driver for j721e EVM (CPB and IVI)")
Signed-off-by: Jayesh Choudhary <j-choudhary@xxxxxx>
---

Error log for J784S4-EVM platform which uses this compatible:
<https://gist.github.com/Jayesh2000/22784d790f493ca182bb78c8d5015c9b>

After this fix, test log for 44100 rate:
<https://gist.github.com/Jayesh2000/13ab5852109f899fa2ceb466f8c130d9>

For rates 8k, 16k, 24k, 32k, 48k, 96k the scki used is the default
value i.e. 24576000 Hz. When any application request sampling rate from
11025, 22050, 44100 or 88200, the clk_set_rate calls are invoked in
j721e_configure_refclk and the scki is modified to 22579200 Hz.

 sound/soc/ti/j721e-evm.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/sound/soc/ti/j721e-evm.c b/sound/soc/ti/j721e-evm.c
index 2057d46ad884..0e7e4ff950b5 100644
--- a/sound/soc/ti/j721e-evm.c
+++ b/sound/soc/ti/j721e-evm.c
@@ -182,6 +182,8 @@ static int j721e_configure_refclk(struct j721e_priv *priv,
 		clk_id = J721E_CLK_PARENT_48000;
 	else if (!(rate % 11025) && priv->pll_rates[J721E_CLK_PARENT_44100])
 		clk_id = J721E_CLK_PARENT_44100;
+	else if (!(rate % 11025) && priv->pll_rates[J721E_CLK_PARENT_48000])
+		clk_id = J721E_CLK_PARENT_48000;
 	else
 		return ret;
 
-- 
2.34.1